383 lines
7.9 KiB
Plaintext
383 lines
7.9 KiB
Plaintext
|
[EFUSE_CFG]
|
||
|
|
########################################################################
|
||
|
|
ef_sf_aes_mode = 0
|
||
|
|
ef_sboot_en = 0
|
||
|
|
ef_dbg_jtag_0_dis = 0
|
||
|
|
ef_dbg_mode = 0
|
||
|
|
###################################################################
|
||
|
|
ef_dbg_pwd_low = 0
|
||
|
|
ef_dbg_pwd_high = 0
|
||
|
|
##########################################
|
||
|
|
sign_cfg = 0
|
||
|
|
################################################################
|
||
|
|
|
||
|
|
ef_key_slot_0_w0 = 0
|
||
|
|
ef_key_slot_0_w1 = 0
|
||
|
|
ef_key_slot_0_w2 = 0
|
||
|
|
ef_key_slot_0_w3 = 0
|
||
|
|
ef_key_slot_1_w0 = 0
|
||
|
|
ef_key_slot_1_w1 = 0
|
||
|
|
ef_key_slot_1_w2 = 0
|
||
|
|
ef_key_slot_1_w3 = 0
|
||
|
|
ef_key_slot_2_w0 = 0
|
||
|
|
ef_key_slot_2_w1 = 0
|
||
|
|
ef_key_slot_2_w2 = 0
|
||
|
|
ef_key_slot_2_w3 = 0
|
||
|
|
ef_key_slot_3_w0 = 0
|
||
|
|
ef_key_slot_3_w1 = 0
|
||
|
|
ef_key_slot_3_w2 = 0
|
||
|
|
ef_key_slot_3_w3 = 0
|
||
|
|
wr_lock_key_slot_0 = 0
|
||
|
|
wr_lock_key_slot_1 = 0
|
||
|
|
wr_lock_key_slot_2 = 0
|
||
|
|
wr_lock_key_slot_3 = 0
|
||
|
|
wr_lock_sw_usage_0 = 0
|
||
|
|
wr_lock_sw_usage_1 = 0
|
||
|
|
wr_lock_sw_usage_2 = 0
|
||
|
|
wr_lock_sw_usage_3 = 0
|
||
|
|
wr_lock_key_slot_11 = 0
|
||
|
|
rd_lock_dbg_pwd = 0
|
||
|
|
rd_lock_key_slot_0 = 0
|
||
|
|
rd_lock_key_slot_1 = 0
|
||
|
|
rd_lock_key_slot_2 = 0
|
||
|
|
rd_lock_key_slot_3 = 0
|
||
|
|
rd_lock_key_slot_11 = 0
|
||
|
|
########################################################################
|
||
|
|
ef_key_slot_4_w0 = 0
|
||
|
|
ef_key_slot_4_w1 = 0
|
||
|
|
ef_key_slot_4_w2 = 0
|
||
|
|
ef_key_slot_4_w3 = 0
|
||
|
|
ef_key_slot_5_w0 = 0
|
||
|
|
ef_key_slot_5_w1 = 0
|
||
|
|
ef_key_slot_5_w2 = 0
|
||
|
|
ef_key_slot_5_w3 = 0
|
||
|
|
ef_key_slot_6_w0 = 0
|
||
|
|
ef_key_slot_6_w1 = 0
|
||
|
|
ef_key_slot_6_w2 = 0
|
||
|
|
ef_key_slot_6_w3 = 0
|
||
|
|
ef_key_slot_7_w0 = 0
|
||
|
|
ef_key_slot_7_w1 = 0
|
||
|
|
ef_key_slot_7_w2 = 0
|
||
|
|
ef_key_slot_7_w3 = 0
|
||
|
|
ef_key_slot_8_w0 = 0
|
||
|
|
ef_key_slot_8_w1 = 0
|
||
|
|
ef_key_slot_8_w2 = 0
|
||
|
|
ef_key_slot_8_w3 = 0
|
||
|
|
ef_key_slot_9_w0 = 0
|
||
|
|
ef_key_slot_9_w1 = 0
|
||
|
|
ef_key_slot_9_w2 = 0
|
||
|
|
ef_key_slot_9_w3 = 0
|
||
|
|
ef_key_slot_10_w0 = 0
|
||
|
|
ef_key_slot_10_w1 = 0
|
||
|
|
ef_key_slot_10_w2 = 0
|
||
|
|
ef_key_slot_10_w3 = 0
|
||
|
|
ef_dat_1_rsvd_0 = 0
|
||
|
|
ef_dat_1_rsvd_1 = 0
|
||
|
|
ef_dat_1_rsvd_2 = 0
|
||
|
|
########################################################################
|
||
|
|
wr_lock_rsvd_2 = 0
|
||
|
|
wr_lock_key_slot_4 = 0
|
||
|
|
wr_lock_key_slot_5 = 0
|
||
|
|
wr_lock_key_slot_6 = 0
|
||
|
|
wr_lock_key_slot_7 = 0
|
||
|
|
wr_lock_key_slot_8 = 0
|
||
|
|
wr_lock_key_slot_9 = 0
|
||
|
|
wr_lock_key_slot_10 = 0
|
||
|
|
wr_lock_dat_1_rsvd_0 = 0
|
||
|
|
wr_lock_dat_1_rsvd_1 = 0
|
||
|
|
wr_lock_dat_1_rsvd_2 = 0
|
||
|
|
rd_lock_key_slot_4 = 0
|
||
|
|
rd_lock_key_slot_5 = 0
|
||
|
|
rd_lock_key_slot_6 = 0
|
||
|
|
rd_lock_key_slot_7 = 0
|
||
|
|
rd_lock_key_slot_8 = 0
|
||
|
|
rd_lock_key_slot_9 = 0
|
||
|
|
rd_lock_key_slot_10 = 0
|
||
|
|
########################################################################
|
||
|
|
ef_zone_00_w0 = 0
|
||
|
|
ef_zone_00_w1 = 0
|
||
|
|
ef_zone_00_w2 = 0
|
||
|
|
ef_zone_00_w3 = 0
|
||
|
|
ef_zone_01_w0 = 0
|
||
|
|
ef_zone_01_w1 = 0
|
||
|
|
ef_zone_01_w2 = 0
|
||
|
|
ef_zone_01_w3 = 0
|
||
|
|
ef_zone_02_w0 = 0
|
||
|
|
ef_zone_02_w1 = 0
|
||
|
|
ef_zone_02_w2 = 0
|
||
|
|
ef_zone_02_w3 = 0
|
||
|
|
ef_zone_03_w0 = 0
|
||
|
|
ef_zone_03_w1 = 0
|
||
|
|
ef_zone_03_w2 = 0
|
||
|
|
ef_zone_03_w3 = 0
|
||
|
|
ef_zone_04_w0 = 0
|
||
|
|
ef_zone_04_w1 = 0
|
||
|
|
ef_zone_04_w2 = 0
|
||
|
|
ef_zone_04_w3 = 0
|
||
|
|
ef_zone_05_w0 = 0
|
||
|
|
ef_zone_05_w1 = 0
|
||
|
|
ef_zone_05_w2 = 0
|
||
|
|
ef_zone_05_w3 = 0
|
||
|
|
ef_zone_06_w0 = 0
|
||
|
|
ef_zone_06_w1 = 0
|
||
|
|
ef_zone_06_w2 = 0
|
||
|
|
ef_zone_06_w3 = 0
|
||
|
|
ef_zone_07_w0 = 0
|
||
|
|
ef_zone_07_w1 = 0
|
||
|
|
ef_zone_07_w2 = 0
|
||
|
|
ef_zone_07_w3 = 0
|
||
|
|
ef_zone_08_w0 = 0
|
||
|
|
ef_zone_08_w1 = 0
|
||
|
|
ef_zone_08_w2 = 0
|
||
|
|
ef_zone_08_w3 = 0
|
||
|
|
ef_zone_09_w0 = 0
|
||
|
|
ef_zone_09_w1 = 0
|
||
|
|
ef_zone_09_w2 = 0
|
||
|
|
ef_zone_09_w3 = 0
|
||
|
|
ef_zone_10_w0 = 0
|
||
|
|
ef_zone_10_w1 = 0
|
||
|
|
ef_zone_10_w2 = 0
|
||
|
|
ef_zone_10_w3 = 0
|
||
|
|
ef_zone_11_w0 = 0
|
||
|
|
ef_zone_11_w1 = 0
|
||
|
|
ef_zone_11_w2 = 0
|
||
|
|
ef_zone_11_w3 = 0
|
||
|
|
ef_zone_12_w0 = 0
|
||
|
|
ef_zone_12_w1 = 0
|
||
|
|
ef_zone_12_w2 = 0
|
||
|
|
ef_zone_12_w3 = 0
|
||
|
|
ef_zone_13_w0 = 0
|
||
|
|
ef_zone_13_w1 = 0
|
||
|
|
ef_zone_13_w2 = 0
|
||
|
|
ef_zone_13_w3 = 0
|
||
|
|
ef_zone_14_w0 = 0
|
||
|
|
ef_zone_14_w1 = 0
|
||
|
|
ef_zone_14_w2 = 0
|
||
|
|
ef_zone_14_w3 = 0
|
||
|
|
ef_zone_15_w0 = 0
|
||
|
|
ef_zone_15_w1 = 0
|
||
|
|
ef_zone_15_w2 = 0
|
||
|
|
ef_zone_15_w3 = 0
|
||
|
|
|
||
|
|
[BOOTHEADER_GROUP0_CFG]
|
||
|
|
magic_code = 0x504e4642
|
||
|
|
revision = 0x01
|
||
|
|
#########################flash cfg#############################
|
||
|
|
flashcfg_magic_code = 0x47464346
|
||
|
|
#flashcfg_magic_code=0
|
||
|
|
io_mode = 0x10
|
||
|
|
#0.5T sfctrl_clk_delay=0 sfctrl_clk_invert=3
|
||
|
|
#1 T sfctrl_clk_delay=1 sfctrl_clk_invert=1
|
||
|
|
#1.5T sfctrl_clk_delay=1 sfctrl_clk_invert=3
|
||
|
|
cont_read_support = 0
|
||
|
|
sfctrl_clk_delay = 1
|
||
|
|
sfctrl_clk_invert = 0x01
|
||
|
|
|
||
|
|
reset_en_cmd = 0x66
|
||
|
|
reset_cmd = 0x99
|
||
|
|
exit_contread_cmd = 0xff
|
||
|
|
exit_contread_cmd_size = 0x3
|
||
|
|
|
||
|
|
jedecid_cmd = 0x9f
|
||
|
|
jedecid_cmd_dmy_clk = 0
|
||
|
|
enter_32bits_addr_cmd = 0xb7
|
||
|
|
exit_32bits_addr_clk = 0xe9
|
||
|
|
|
||
|
|
sector_size = 4
|
||
|
|
mfg_id = 0xff
|
||
|
|
page_size = 256
|
||
|
|
|
||
|
|
chip_erase_cmd = 0xc7
|
||
|
|
sector_erase_cmd = 0x20
|
||
|
|
blk32k_erase_cmd = 0x52
|
||
|
|
blk64k_erase_cmd = 0xd8
|
||
|
|
|
||
|
|
write_enable_cmd = 0x06
|
||
|
|
page_prog_cmd = 0x02
|
||
|
|
qpage_prog_cmd = 0x32
|
||
|
|
qual_page_prog_addr_mode = 0
|
||
|
|
|
||
|
|
fast_read_cmd = 0x0b
|
||
|
|
fast_read_dmy_clk = 1
|
||
|
|
qpi_fast_read_cmd = 0x0b
|
||
|
|
qpi_fast_read_dmy_clk = 1
|
||
|
|
|
||
|
|
fast_read_do_cmd = 0x3b
|
||
|
|
fast_read_do_dmy_clk = 1
|
||
|
|
fast_read_dio_cmd = 0xbb
|
||
|
|
fast_read_dio_dmy_clk = 0
|
||
|
|
|
||
|
|
fast_read_qo_cmd = 0x6b
|
||
|
|
fast_read_qo_dmy_clk = 1
|
||
|
|
fast_read_qio_cmd = 0xeb
|
||
|
|
fast_read_qio_dmy_clk = 2
|
||
|
|
|
||
|
|
qpi_fast_read_qio_cmd = 0xeb
|
||
|
|
qpi_fast_read_qio_dmy_clk = 2
|
||
|
|
qpi_page_prog_cmd = 0x02
|
||
|
|
write_vreg_enable_cmd = 0x50
|
||
|
|
|
||
|
|
wel_reg_index = 0
|
||
|
|
qe_reg_index = 1
|
||
|
|
busy_reg_index = 0
|
||
|
|
wel_bit_pos = 1
|
||
|
|
|
||
|
|
qe_bit_pos = 1
|
||
|
|
busy_bit_pos = 0
|
||
|
|
wel_reg_write_len = 2
|
||
|
|
wel_reg_read_len = 1
|
||
|
|
|
||
|
|
qe_reg_write_len = 2
|
||
|
|
qe_reg_read_len = 1
|
||
|
|
release_power_down = 0xab
|
||
|
|
busy_reg_read_len = 1
|
||
|
|
|
||
|
|
reg_read_cmd0 = 0x05
|
||
|
|
reg_read_cmd1 = 0x35
|
||
|
|
|
||
|
|
reg_write_cmd0 = 0x01
|
||
|
|
reg_write_cmd1 = 0x01
|
||
|
|
|
||
|
|
enter_qpi_cmd = 0x38
|
||
|
|
exit_qpi_cmd = 0xff
|
||
|
|
cont_read_code = 0x20
|
||
|
|
cont_read_exit_code = 0xf0
|
||
|
|
|
||
|
|
burst_wrap_cmd = 0x77
|
||
|
|
burst_wrap_dmy_clk = 0x03
|
||
|
|
burst_wrap_data_mode = 2
|
||
|
|
burst_wrap_code = 0x40
|
||
|
|
|
||
|
|
de_burst_wrap_cmd = 0x77
|
||
|
|
de_burst_wrap_cmd_dmy_clk = 0x03
|
||
|
|
de_burst_wrap_code_mode = 2
|
||
|
|
de_burst_wrap_code = 0xf0
|
||
|
|
|
||
|
|
sector_erase_time = 300
|
||
|
|
blk32k_erase_time = 1200
|
||
|
|
|
||
|
|
blk64k_erase_time = 1200
|
||
|
|
|
||
|
|
page_prog_time = 50
|
||
|
|
|
||
|
|
chip_erase_time = 200000
|
||
|
|
power_down_delay = 20
|
||
|
|
qe_data = 0
|
||
|
|
|
||
|
|
flashcfg_crc32 = 0
|
||
|
|
|
||
|
|
#########################clk cfg#####################################
|
||
|
|
clkcfg_magic_code = 0x47464350
|
||
|
|
#clkcfg_magic_code=0
|
||
|
|
|
||
|
|
#0:None,1:24M,2:32M,3:38.4M,4:40M,5:26M,6:RC32M
|
||
|
|
xtal_type = 7
|
||
|
|
#mcu_clk 0:RC32M;1:XTAL;2:aupll_div2;3:aupll_div1;4:wifipll_240M;5:wifipll_320M
|
||
|
|
mcu_clk = 5
|
||
|
|
mcu_clk_div = 0
|
||
|
|
mcu_bclk_div = 0
|
||
|
|
mcu_pbclk_div = 3
|
||
|
|
|
||
|
|
#0:mcu pbclk,1:cpupll 200M,2:wifipll 320M,3:cpupll 400M
|
||
|
|
emi_clk = 2
|
||
|
|
emi_clk_div = 1
|
||
|
|
|
||
|
|
#flash_clk_type 0:wifipll_120M;1:xtal;2:aupll_div5;3:muxpll_80M;4:bclk;5:wifipll_96M
|
||
|
|
flash_clk_type = 1
|
||
|
|
flash_clk_div = 0
|
||
|
|
|
||
|
|
wifipll_pu = 1
|
||
|
|
aupll_pu = 1
|
||
|
|
|
||
|
|
rsvd0 = 0
|
||
|
|
|
||
|
|
clkcfg_crc32 = 0
|
||
|
|
|
||
|
|
########################boot cfg#####################################
|
||
|
|
#1:ECC
|
||
|
|
sign = 0
|
||
|
|
#1:AES128 CTR,2:AES256 CTR,3:AES192 CTR,4:AES128 XTS
|
||
|
|
encrypt_type = 0
|
||
|
|
key_sel = 0
|
||
|
|
xts_mode = 0
|
||
|
|
aes_region_lock = 0
|
||
|
|
no_segment = 1
|
||
|
|
boot2_enable = 0
|
||
|
|
boot2_rollback = 0
|
||
|
|
cpu_master_id = 0
|
||
|
|
notload_in_bootrom = 0
|
||
|
|
crc_ignore = 0
|
||
|
|
hash_ignore = 0
|
||
|
|
power_on_mm = 1
|
||
|
|
em_sel = 1
|
||
|
|
cmds_en = 1
|
||
|
|
#0:cmds bypass wrap commands to macro, original mode;
|
||
|
|
#1:cmds handle wrap commands, original mode;
|
||
|
|
#2:cmds bypass wrap commands to macro, cmds force wrap16*4 splitted into two wrap8*4;
|
||
|
|
#3:cmds handle wrap commands, cmds force wrap16*4 splitted into two wrap8*4
|
||
|
|
cmds_wrap_mode = 2
|
||
|
|
#0:SF_CTRL_WRAP_LEN_8, 1:SF_CTRL_WRAP_LEN_16, 2:SF_CTRL_WRAP_LEN_32,
|
||
|
|
#3:SF_CTRL_WRAP_LEN_64, 9: SF_CTRL_WRAP_LEN_4096
|
||
|
|
cmds_wrap_len = 2
|
||
|
|
icache_invalid = 1
|
||
|
|
dcache_invalid = 1
|
||
|
|
fpga_halt_release = 0
|
||
|
|
|
||
|
|
########################image cfg####################################
|
||
|
|
#flash controller offset
|
||
|
|
group_image_offset = 0x2000
|
||
|
|
aes_region_len = 0
|
||
|
|
|
||
|
|
#total image len or segment count
|
||
|
|
img_len_cnt = 0x100
|
||
|
|
#img hash
|
||
|
|
hash_0 = 0xdeadbeef
|
||
|
|
hash_1 = 0
|
||
|
|
hash_2 = 0
|
||
|
|
hash_3 = 0
|
||
|
|
hash_4 = 0
|
||
|
|
hash_5 = 0
|
||
|
|
hash_6 = 0
|
||
|
|
hash_7 = 0
|
||
|
|
|
||
|
|
########################CPU M0 cfg###################################
|
||
|
|
m0_config_enable = 1
|
||
|
|
m0_halt_cpu = 0
|
||
|
|
m0_cache_enable = 0
|
||
|
|
m0_cache_wa = 0
|
||
|
|
m0_cache_wb = 0
|
||
|
|
m0_cache_wt = 0
|
||
|
|
m0_cache_way_dis = 0
|
||
|
|
m0_reserved = 0
|
||
|
|
|
||
|
|
#img RAM address or flash offset
|
||
|
|
m0_image_address_offset = 0x0
|
||
|
|
m0_boot_entry = 0xA0000000
|
||
|
|
m0_msp_val = 0
|
||
|
|
|
||
|
|
boot2_pt_table_0 = 0
|
||
|
|
boot2_pt_table_1 = 0
|
||
|
|
|
||
|
|
flashCfgTableAddr = 0
|
||
|
|
flashCfgTableLen = 0
|
||
|
|
|
||
|
|
########################patch on read################################
|
||
|
|
patch_read_addr0 = 0
|
||
|
|
patch_read_value0 = 0
|
||
|
|
patch_read_addr1 = 0
|
||
|
|
patch_read_value1 = 0
|
||
|
|
patch_read_addr2 = 0
|
||
|
|
patch_read_value2 = 0
|
||
|
|
|
||
|
|
########################patch on jump################################
|
||
|
|
patch_jump_addr0 = 0
|
||
|
|
patch_jump_value0 = 0
|
||
|
|
patch_jump_addr1 = 0
|
||
|
|
patch_jump_value1 = 0
|
||
|
|
patch_jump_addr2 = 0
|
||
|
|
patch_jump_value2 = 0
|
||
|
|
|
||
|
|
reserved = 0
|
||
|
|
|
||
|
|
crc32 = 0xdeadbeef
|