add chip configuration from Bouffalo Lab
This commit is contained in:
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57a2f84880
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BIN
chips/bl602/eflash_loader/eflash_loader.elf
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BIN
chips/bl602/eflash_loader/eflash_loader.elf
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chips/bl602/eflash_loader/eflash_loader.map
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11579
chips/bl602/eflash_loader/eflash_loader.map
Normal file
File diff suppressed because it is too large
Load Diff
BIN
chips/bl602/eflash_loader/eflash_loader_24m.bin
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chips/bl602/eflash_loader/eflash_loader_24m.bin
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chips/bl602/eflash_loader/eflash_loader_26m.bin
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chips/bl602/eflash_loader/eflash_loader_26m.bin
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chips/bl602/eflash_loader/eflash_loader_32m.bin
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chips/bl602/eflash_loader/eflash_loader_32m.bin
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chips/bl602/eflash_loader/eflash_loader_38p4m.bin
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chips/bl602/eflash_loader/eflash_loader_38p4m.bin
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chips/bl602/eflash_loader/eflash_loader_40m.bin
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chips/bl602/eflash_loader/eflash_loader_40m.bin
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chips/bl602/eflash_loader/eflash_loader_cfg.conf
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chips/bl602/eflash_loader/eflash_loader_cfg.conf
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@ -0,0 +1,65 @@
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[LOAD_CFG]
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#jlink or uart
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interface = uart
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device = COM1
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speed_uart_boot = 500000
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speed_uart_load = 500000
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speed_jlink = 2000
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#cklink usb vid|pid
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cklink_vidpid = 42bf|b210
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cklink_type = CKLink_Lite_Vendor-rog
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#eg: rv_dbg_plus, ft2232hl, ft2232d
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openocd_config = rv_dbg_plus
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#0:without load, 1:eflash_loader load
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load_function = 1
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auto_burn = false
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do_reset = true
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#reset retry+reset hold time
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reset_hold_time = 5
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shake_hand_delay = 100
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reset_revert = false
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#cutoff revert+cutoff time
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cutoff_time = 100
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shake_hand_retry = 2
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flash_burn_retry = 1
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checksum_err_retry = 3
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#1:24M, 2:32M, 3:38.4M, 4:40M, 5:26M, 6:RC32M
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#xtal_type = 4
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erase_time_out = 15000
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#chiptype=602
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eflash_loader_file = chips/bl602/eflash_loader/eflash_loader_40m.bin
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check_mac = true
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#0:no erase,1:programmed section erase,2:chip erase
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erase = 1
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# switch eflash_loader command log save
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local_log = false
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#0:verify by calculating SHA256(xip), >0:read back verify and verify by calculating SHA256(sbus)
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verify = 0
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tx_size = 2056
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cpu_reset_after_load = false
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#skip mode set first para is skip addr, second para is skip len
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skip_mode = 0x0, 0x0
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boot2_isp_mode = 0
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isp_mode_speed = 2000000
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isp_shakehand_timeout = 0
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[FLASH_CFG]
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flash_id = ef4015
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flash_clock_cfg = 1
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#0:NIO, 1:DO, 2:QO, 3:DIO, 4:QIO
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flash_io_mode = 1
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#empty: auto,0: internal flash with io switch,1: internal flash no io switch,2: GPIO 17-22,3: GPIO 0-2&20-22
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flash_pin = ""
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#empty for auto, otherwise specified para file path: eg: chips/bl602/efuse_bootheader/flash_para.bin
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flash_para = chips/bl602/efuse_bootheader/flash_para.bin
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decompress_write = true
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file = chips/bl602/img_create/bootinfo_boot2.bin chips/bl602/img_create/img_boot2.bin chips/bl602/partition/partition.bin chips/bl602/partition/partition.bin
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address = 00000000 00002000 e000 f000
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[EFUSE_CFG]
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burn_en = true
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factory_mode = false
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security_write = false
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security_save = true
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file = ../../../Tools/img_tools/efuse_bootheader/efusedata.bin
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maskfile = ../../../Tools/img_tools/efuse_bootheader/efusedata_mask.bin
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65
chips/bl602/eflash_loader/eflash_loader_cfg.ini
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chips/bl602/eflash_loader/eflash_loader_cfg.ini
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@ -0,0 +1,65 @@
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[LOAD_CFG]
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#jlink or uart
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interface = uart
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device = COM1
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speed_uart_boot = 500000
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speed_uart_load = 500000
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speed_jlink = 2000
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#cklink usb vid|pid
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cklink_vidpid = 42bf|b210
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cklink_type = CKLink_Lite_Vendor-rog
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#eg: rv_dbg_plus, ft2232hl, ft2232d
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openocd_config = rv_dbg_plus
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#0:without load, 1:eflash_loader load
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load_function = 1
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auto_burn = false
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do_reset = true
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#reset retry+reset hold time
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reset_hold_time = 5
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shake_hand_delay = 100
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reset_revert = false
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#cutoff revert+cutoff time
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cutoff_time = 100
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shake_hand_retry = 2
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flash_burn_retry = 1
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checksum_err_retry = 3
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#1:24M, 2:32M, 3:38.4M, 4:40M, 5:26M, 6:RC32M
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#xtal_type = 4
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erase_time_out = 15000
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#chiptype=602
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eflash_loader_file = chips/bl602/eflash_loader/eflash_loader_40m.bin
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check_mac = true
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#0:no erase,1:programmed section erase,2:chip erase
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erase = 1
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# switch eflash_loader command log save
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local_log = false
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#0:verify by calculating SHA256(xip), >0:read back verify and verify by calculating SHA256(sbus)
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verify = 0
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tx_size = 2056
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cpu_reset_after_load = false
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#skip mode set first para is skip addr, second para is skip len
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skip_mode = 0x0, 0x0
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boot2_isp_mode = 0
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isp_mode_speed = 2000000
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isp_shakehand_timeout = 0
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[FLASH_CFG]
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flash_id = ef4015
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flash_clock_cfg = 1
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#0:NIO, 1:DO, 2:QO, 3:DIO, 4:QIO
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flash_io_mode = 1
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#empty: auto,0: internal flash with io switch,1: internal flash no io switch,2: GPIO 17-22,3: GPIO 0-2&20-22
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flash_pin =
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#empty for auto, otherwise specified para file path: eg: chips/bl602/efuse_bootheader/flash_para.bin
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flash_para = chips/bl602/efuse_bootheader/flash_para.bin
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decompress_write = true
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file =
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address =
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[EFUSE_CFG]
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burn_en = true
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factory_mode = false
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security_write = false
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security_save = true
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file = ../../../Tools/img_tools/efuse_bootheader/efusedata.bin
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maskfile = ../../../Tools/img_tools/efuse_bootheader/efusedata_mask.bin
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196
chips/bl602/efuse_bootheader/efuse_bootheader_cfg.conf
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chips/bl602/efuse_bootheader/efuse_bootheader_cfg.conf
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[EFUSE_CFG]
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########################################################################
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#2bits
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ef_sf_aes_mode = 0
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#2bits
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ef_sboot_sign_mode = 0
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#2bits
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ef_sboot_en = 0
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#2bits
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ef_dbg_jtag_dis = 0
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#4bits
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ef_dbg_mode = 0
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#32bits
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ef_dbg_pwd_low = 0
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#32bits
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ef_dbg_pwd_high = 0
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#2bits
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flash_pwr_delay = 0
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###################################################################
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ef_key_slot_2_w0 = 0
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ef_key_slot_2_w1 = 0
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ef_key_slot_2_w2 = 0
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ef_key_slot_2_w3 = 0
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ef_key_slot_3_w0 = 0
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ef_key_slot_3_w1 = 0
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ef_key_slot_3_w2 = 0
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ef_key_slot_3_w3 = 0
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ef_key_slot_4_w0 = 0
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ef_key_slot_4_w1 = 0
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ef_key_slot_4_w2 = 0
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ef_key_slot_4_w3 = 0
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wr_lock_key_slot_4_l = 0
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wr_lock_dbg_pwd = 0
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wr_lock_key_slot_2 = 0
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wr_lock_key_slot_3 = 0
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wr_lock_key_slot_4_h = 0
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rd_lock_dbg_pwd = 0
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rd_lock_key_slot_2 = 0
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rd_lock_key_slot_3 = 0
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rd_lock_key_slot_4 = 0
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[BOOTHEADER_CFG]
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magic_code = 0x504e4642
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revision = 0x01
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#########################flash cfg#############################
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flashcfg_magic_code = 0x47464346
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#flashcfg_magic_code=0
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io_mode = 0x10
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cont_read_support = 0
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#0.5T sfctrl_clk_delay=0 sfctrl_clk_invert=3
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#1 T sfctrl_clk_delay=1 sfctrl_clk_invert=1
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#1.5T sfctrl_clk_delay=1 sfctrl_clk_invert=3
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sfctrl_clk_delay = 1
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sfctrl_clk_invert = 0x01
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reset_en_cmd = 0x66
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reset_cmd = 0x99
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exit_contread_cmd = 0xff
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exit_contread_cmd_size = 3
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jedecid_cmd = 0x9f
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jedecid_cmd_dmy_clk = 0
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qpi_jedecid_cmd = 0x9f
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qpi_jedecid_dmy_clk = 0
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sector_size = 4
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mfg_id = 0xff
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page_size = 256
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chip_erase_cmd = 0xc7
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sector_erase_cmd = 0x20
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blk32k_erase_cmd = 0x52
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blk64k_erase_cmd = 0xd8
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write_enable_cmd = 0x06
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page_prog_cmd = 0x02
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qpage_prog_cmd = 0x32
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qual_page_prog_addr_mode = 0
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fast_read_cmd = 0x0b
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fast_read_dmy_clk = 1
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qpi_fast_read_cmd = 0x0b
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qpi_fast_read_dmy_clk = 1
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fast_read_do_cmd = 0x3b
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fast_read_do_dmy_clk = 1
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fast_read_dio_cmd = 0xbb
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fast_read_dio_dmy_clk = 0
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fast_read_qo_cmd = 0x6b
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fast_read_qo_dmy_clk = 1
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fast_read_qio_cmd = 0xeb
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fast_read_qio_dmy_clk = 2
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qpi_fast_read_qio_cmd = 0xeb
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qpi_fast_read_qio_dmy_clk = 2
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qpi_page_prog_cmd = 0x02
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write_vreg_enable_cmd = 0x50
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wel_reg_index = 0
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qe_reg_index = 1
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busy_reg_index = 0
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wel_bit_pos = 1
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qe_bit_pos = 1
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busy_bit_pos = 0
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wel_reg_write_len = 2
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wel_reg_read_len = 1
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qe_reg_write_len = 2
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qe_reg_read_len = 1
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release_power_down = 0xab
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busy_reg_read_len = 1
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reg_read_cmd0 = 0x05
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reg_read_cmd1 = 0x35
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reg_write_cmd0 = 0x01
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reg_write_cmd1 = 0x01
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enter_qpi_cmd = 0x38
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exit_qpi_cmd = 0xff
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cont_read_code = 0xa0
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cont_read_exit_code = 0xff
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burst_wrap_cmd = 0x77
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burst_wrap_dmy_clk = 0x03
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burst_wrap_data_mode = 2
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burst_wrap_code = 0x40
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de_burst_wrap_cmd = 0x77
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de_burst_wrap_cmd_dmy_clk = 0x03
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de_burst_wrap_code_mode = 2
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de_burst_wrap_code = 0xF0
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sector_erase_time = 300
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blk32k_erase_time = 1200
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blk64k_erase_time = 1200
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page_prog_time = 5
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chip_erase_time = 200000
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power_down_delay = 20
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qe_data = 0
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flashcfg_crc32 = 0
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#########################clk cfg####################################
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clkcfg_magic_code = 0x47464350
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#clkcfg_magic_code=0
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#0:Not use XTAL to set PLL,1:XTAL is 24M ,2:XTAL is 32M ,3:XTAL is 38.4M
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#4:XTAL is 40M,5:XTAL is 26M,6:XTAL is RC32M
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xtal_type = 4
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#0:RC32M,1:XTAL,2:PLL 48M,3:PLL 120M,4:PLL 160M,5:PLL 192M
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pll_clk = 4
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hclk_div = 0
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bclk_div = 1
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#0:120M,1:XCLK(RC32M or XTAL),2:48M,3:80M,4:BCLK,5:96M
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flash_clk_type = 3
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flash_clk_div = 1
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clkcfg_crc32 = 0
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########################boot cfg####################################
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#1:ECC
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sign = 0
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#1:AES128,2:AES256,3:AES192
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encrypt_type = 0
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key_sel = 0
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no_segment = 1
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cache_enable = 1
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notload_in_bootrom = 0
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aes_region_lock = 0
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cache_way_disable = 0x03
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crc_ignore = 0
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hash_ignore = 0
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########################image cfg####################################
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#total image len or segment count
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img_len = 0x100
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bootentry = 0
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#img RAM address or flash offset
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img_start = 0x2000
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#img hash
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hash_0 = 0xdeadbeef
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hash_1 = 0
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hash_2 = 0
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hash_3 = 0
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hash_4 = 0
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hash_5 = 0
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hash_6 = 0
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hash_7 = 0
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crc32 = 0xdeadbeef
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0
chips/bl602/img_create/whole_flash_data.bin
Normal file
0
chips/bl602/img_create/whole_flash_data.bin
Normal file
BIN
chips/bl602/img_create/whole_img.pack
Normal file
BIN
chips/bl602/img_create/whole_img.pack
Normal file
Binary file not shown.
69
chips/bl606p/eflash_loader/eflash_loader_cfg.conf
Normal file
69
chips/bl606p/eflash_loader/eflash_loader_cfg.conf
Normal file
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[LOAD_CFG]
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#jlink or uart
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interface = uart
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device = COM1
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speed_uart_boot = 500000
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speed_uart_load = 2000000
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#cklink usb vid|pid
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cklink_vidpid = 42bf|b210
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cklink_type = CKLink_Lite_Vendor-rog
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#eg: rv_dbg_plus, ft2232hl, ft2232d
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openocd_config = rv_dbg_plus
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auto_burn = false
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speed_jlink = 1000
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#0:without load, 1:eflash_loader load, 2: bootrom load
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load_function = 2
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do_reset = true
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#reset retry+hold time
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reset_hold_time = 50
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shake_hand_delay = 100
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reset_revert = false
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cutoff_time = 50
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shake_hand_retry = 3
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flash_burn_retry = 1
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checksum_err_retry = 3
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erase_time_out = 100000
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#chiptype=bl606p
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check_mac = true
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#0:no erase,1:programmed section erase,2:chip erase
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erase = 1
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# switch eflash_loader command log save
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local_log = false
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#0:verify by calculating SHA256(xip), >0:read back verify and verify by calculating SHA256(sbus)
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verify = 0
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tx_size = 4104
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cpu_reset_after_load = false
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#empty for auto, otherwise specified clock para file path: eg: chips/bl606p/efuse_bootheader/clock_para.bin
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clock_para = chips/bl606p/efuse_bootheader/clock_para.bin
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#skip mode set first para is skip addr, second para is skip len
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skip_mode = 0x0, 0x0
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boot2_isp_mode = 0
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isp_mode_speed = 2000000
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isp_shakehand_timeout = 0
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[FLASH_CFG]
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flash_id = ef4016
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#bit 7-4 flash_clock_type: 0:120M wifipll, 1:xtal, 2:128M cpupll, 3:80M wifipll, 4:bclk, 5:96M wifipll
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#bit 3-0 flash_clock_div
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flash_clock_cfg = 0x41
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#0:0.5T delay, 1:1T delay, 2:1.5T delay, 3:2T delay
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flash_clock_delay = 0
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#0:NIO, 1:DO, 2:QO, 3:DIO, 4:QIO
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flash_io_mode = 1
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#flash_pin value:
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#bit 7 flash pin autoscan
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#bit 6-0 flash pin cfg: 0: internal swap io0 with io3, 2: internal no swap io0 with io3, 4: external gpi34-39,
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flash_pin = 0x80
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#empty for auto, otherwise specified flash para file path: eg: chips/bl606p/efuse_bootheader/flash_para.bin
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flash_para = chips/bl606p/efuse_bootheader/flash_para.bin
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decompress_write = false
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file = chips/bl606p/img_create2/whole_img.bin
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address = 00000000
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[EFUSE_CFG]
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burn_en = true
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factory_mode = false
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security_write = false
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security_save = true
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file = ../../../Tools/img_tools/efuse_bootheader/efusedata.bin
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maskfile = ../../../Tools/img_tools/efuse_bootheader/efusedata_mask.bin
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520
chips/bl606p/efuse_bootheader/efuse_bootheader_cfg.conf
Normal file
520
chips/bl606p/efuse_bootheader/efuse_bootheader_cfg.conf
Normal file
|
|
@ -0,0 +1,520 @@
|
|||
[EFUSE_CFG]
|
||||
########################################################################
|
||||
ef_sf_aes_mode=0
|
||||
ef_no_xtal=0
|
||||
ef_force_no_trim=0
|
||||
ef_sf_key_re_sel=0
|
||||
ef_dbg_jtag_0_dis=0
|
||||
###################################################################
|
||||
ef_dbg_pwd_low=0
|
||||
ef_dbg_pwd_high=0
|
||||
ef_dbg_pwd2_low=0
|
||||
ef_dbg_pwd2_high=0
|
||||
ef_wifi_mac_low=0
|
||||
ef_wifi_mac_high=0
|
||||
ef_key_slot_0_w0=0
|
||||
ef_key_slot_0_w1=0
|
||||
ef_key_slot_0_w2=0
|
||||
ef_key_slot_0_w3=0
|
||||
ef_key_slot_1_w0=0
|
||||
ef_key_slot_1_w1=0
|
||||
ef_key_slot_1_w2=0
|
||||
ef_key_slot_1_w3=0
|
||||
ef_key_slot_2_w0=0
|
||||
ef_key_slot_2_w1=0
|
||||
ef_key_slot_2_w2=0
|
||||
ef_key_slot_2_w3=0
|
||||
ef_key_slot_3_w0=0
|
||||
ef_key_slot_3_w1=0
|
||||
ef_key_slot_3_w2=0
|
||||
ef_key_slot_3_w3=0
|
||||
##########################################
|
||||
ef_sw_usage_0=0
|
||||
ef_sw_usage_1=0
|
||||
ef_sw_usage_2=0
|
||||
ef_sw_usage_3=0
|
||||
ef_key_slot_11_w0=0
|
||||
ef_key_slot_11_w1=0
|
||||
ef_key_slot_11_w2=0
|
||||
ef_key_slot_11_w3=0
|
||||
###################################################################
|
||||
ef_sec_lifecycle=0
|
||||
wr_lock_rsvd_0=0
|
||||
wr_lock_boot_mode=0
|
||||
wr_lock_dbg_pwd=0
|
||||
wr_lock_wifi_mac=0
|
||||
wr_lock_key_slot_0=0
|
||||
wr_lock_key_slot_1=0
|
||||
wr_lock_key_slot_2=0
|
||||
wr_lock_key_slot_3=0
|
||||
wr_lock_sw_usage_0=0
|
||||
wr_lock_sw_usage_1=0
|
||||
wr_lock_sw_usage_2=0
|
||||
wr_lock_sw_usage_3=0
|
||||
wr_lock_key_slot_11=0
|
||||
rd_lock_dbg_pwd=0
|
||||
rd_lock_key_slot_0=0
|
||||
rd_lock_key_slot_1=0
|
||||
rd_lock_key_slot_2=0
|
||||
rd_lock_key_slot_3=0
|
||||
rd_lock_key_slot_11=0
|
||||
########################################################################
|
||||
ef_key_slot_4_w0=0
|
||||
ef_key_slot_4_w1=0
|
||||
ef_key_slot_4_w2=0
|
||||
ef_key_slot_4_w3=0
|
||||
ef_key_slot_5_w0=0
|
||||
ef_key_slot_5_w1=0
|
||||
ef_key_slot_5_w2=0
|
||||
ef_key_slot_5_w3=0
|
||||
ef_key_slot_6_w0=0
|
||||
ef_key_slot_6_w1=0
|
||||
ef_key_slot_6_w2=0
|
||||
ef_key_slot_6_w3=0
|
||||
ef_key_slot_7_w0=0
|
||||
ef_key_slot_7_w1=0
|
||||
ef_key_slot_7_w2=0
|
||||
ef_key_slot_7_w3=0
|
||||
ef_key_slot_8_w0=0
|
||||
ef_key_slot_8_w1=0
|
||||
ef_key_slot_8_w2=0
|
||||
ef_key_slot_8_w3=0
|
||||
ef_key_slot_9_w0=0
|
||||
ef_key_slot_9_w1=0
|
||||
ef_key_slot_9_w2=0
|
||||
ef_key_slot_9_w3=0
|
||||
ef_key_slot_10_w0=0
|
||||
ef_key_slot_10_w1=0
|
||||
ef_key_slot_10_w2=0
|
||||
ef_key_slot_10_w3=0
|
||||
ef_dat_1_rsvd_0=0
|
||||
ef_dat_1_rsvd_1=0
|
||||
ef_dat_1_rsvd_2=0
|
||||
########################################################################
|
||||
wr_lock_rsvd_1=0
|
||||
wr_lock_key_slot_4=0
|
||||
wr_lock_key_slot_5=0
|
||||
wr_lock_key_slot_6=0
|
||||
wr_lock_key_slot_7=0
|
||||
wr_lock_key_slot_8=0
|
||||
wr_lock_key_slot_9=0
|
||||
wr_lock_key_slot_10=0
|
||||
wr_lock_dat_1_rsvd_0=0
|
||||
wr_lock_dat_1_rsvd_1=0
|
||||
wr_lock_dat_1_rsvd_2=0
|
||||
rd_lock_key_slot_4=0
|
||||
rd_lock_key_slot_5=0
|
||||
rd_lock_key_slot_6=0
|
||||
rd_lock_key_slot_7=0
|
||||
rd_lock_key_slot_8=0
|
||||
rd_lock_key_slot_9=0
|
||||
rd_lock_key_slot_10=0
|
||||
|
||||
[BOOTHEADER_GROUP0_CFG]
|
||||
magic_code=0x504e4642
|
||||
revision=0x01
|
||||
#########################flash cfg#############################
|
||||
flashcfg_magic_code=0x47464346
|
||||
#flashcfg_magic_code=0
|
||||
io_mode=0x10
|
||||
#0.5T sfctrl_clk_delay=0 sfctrl_clk_invert=3
|
||||
#1 T sfctrl_clk_delay=1 sfctrl_clk_invert=1
|
||||
#1.5T sfctrl_clk_delay=1 sfctrl_clk_invert=3
|
||||
cont_read_support=0
|
||||
sfctrl_clk_delay=1
|
||||
sfctrl_clk_invert=0x01
|
||||
|
||||
reset_en_cmd=0x66
|
||||
reset_cmd=0x99
|
||||
exit_contread_cmd=0xff
|
||||
exit_contread_cmd_size=0x3
|
||||
|
||||
jedecid_cmd=0x9f
|
||||
jedecid_cmd_dmy_clk=0
|
||||
enter_32bits_addr_cmd=0xb7
|
||||
exit_32bits_addr_clk=0xe9
|
||||
|
||||
sector_size=4
|
||||
mfg_id=0xff
|
||||
page_size=256
|
||||
|
||||
chip_erase_cmd=0xc7
|
||||
sector_erase_cmd=0x20
|
||||
blk32k_erase_cmd=0x52
|
||||
blk64k_erase_cmd=0xd8
|
||||
|
||||
write_enable_cmd=0x06
|
||||
page_prog_cmd=0x02
|
||||
qpage_prog_cmd=0x32
|
||||
qual_page_prog_addr_mode=0
|
||||
|
||||
fast_read_cmd=0x0b
|
||||
fast_read_dmy_clk=1
|
||||
qpi_fast_read_cmd=0x0b
|
||||
qpi_fast_read_dmy_clk=1
|
||||
|
||||
fast_read_do_cmd=0x3b
|
||||
fast_read_do_dmy_clk=1
|
||||
fast_read_dio_cmd=0xbb
|
||||
fast_read_dio_dmy_clk=0
|
||||
|
||||
fast_read_qo_cmd=0x6b
|
||||
fast_read_qo_dmy_clk=1
|
||||
fast_read_qio_cmd=0xeb
|
||||
fast_read_qio_dmy_clk=2
|
||||
|
||||
qpi_fast_read_qio_cmd=0xeb
|
||||
qpi_fast_read_qio_dmy_clk=2
|
||||
qpi_page_prog_cmd=0x02
|
||||
write_vreg_enable_cmd=0x50
|
||||
|
||||
wel_reg_index=0
|
||||
qe_reg_index=1
|
||||
busy_reg_index=0
|
||||
wel_bit_pos=1
|
||||
|
||||
qe_bit_pos=1
|
||||
busy_bit_pos=0
|
||||
wel_reg_write_len=2
|
||||
wel_reg_read_len=1
|
||||
|
||||
qe_reg_write_len=2
|
||||
qe_reg_read_len=1
|
||||
release_power_down = 0xab
|
||||
busy_reg_read_len=1
|
||||
|
||||
reg_read_cmd0=0x05
|
||||
reg_read_cmd1=0x35
|
||||
|
||||
reg_write_cmd0=0x01
|
||||
reg_write_cmd1=0x01
|
||||
|
||||
enter_qpi_cmd=0x38
|
||||
exit_qpi_cmd=0xff
|
||||
cont_read_code=0x20
|
||||
cont_read_exit_code=0xf0
|
||||
|
||||
burst_wrap_cmd=0x77
|
||||
burst_wrap_dmy_clk=0x03
|
||||
burst_wrap_data_mode=2
|
||||
burst_wrap_code=0x40
|
||||
|
||||
de_burst_wrap_cmd=0x77
|
||||
de_burst_wrap_cmd_dmy_clk=0x03
|
||||
de_burst_wrap_code_mode=2
|
||||
de_burst_wrap_code=0xf0
|
||||
|
||||
sector_erase_time=300
|
||||
blk32k_erase_time=1200
|
||||
|
||||
blk64k_erase_time=1200
|
||||
|
||||
page_prog_time=50
|
||||
|
||||
chip_erase_time=200000
|
||||
power_down_delay = 20
|
||||
qe_data = 0
|
||||
|
||||
flashcfg_crc32=0
|
||||
|
||||
#########################clk cfg#####################################
|
||||
clkcfg_magic_code=0x47464350
|
||||
#clkcfg_magic_code=0
|
||||
|
||||
#0:None,1:24M,2:32M,3:38.4M,4:40M,5:26M,6:RC32M
|
||||
xtal_type=4
|
||||
#0:RC32M,1:Xtal,2:cpupll 400M,3:wifipll 192M,4:wifipll 320M
|
||||
mcu_clk=4
|
||||
mcu_clk_div=0
|
||||
mcu_bclk_div=0
|
||||
mcu_pbclk_div=3
|
||||
|
||||
lp_div=1
|
||||
|
||||
#0:RC32M,1:Xtal,2:wifipll 240M,3:wifipll 320M,4:cpupll 400M
|
||||
dsp_clk=3
|
||||
dsp_clk_div=0
|
||||
dsp_bclk_div=1
|
||||
#0:RC32M,1:Xtal,2:wifipll 160M,3:cpupll 160M,4:wifipll 240M
|
||||
dsp_pbclk=2
|
||||
dsp_pbclk_div=0
|
||||
|
||||
#0:mcu pbclk,1:cpupll 200M,2:wifipll 320M,3:cpupll 400M
|
||||
emi_clk=2
|
||||
emi_clk_div=1
|
||||
|
||||
#0:wifipll 120M,1:xtal,2:cpupll 100M,3:wifipll 80M,4:bclk,5:wifipll 96M
|
||||
flash_clk_type=1
|
||||
flash_clk_div=0
|
||||
|
||||
wifipll_pu=1
|
||||
aupll_pu=1
|
||||
cpupll_pu=1
|
||||
mipipll_pu=1
|
||||
uhspll_pu=1
|
||||
|
||||
clkcfg_crc32=0
|
||||
|
||||
########################boot cfg#####################################
|
||||
#1:ECC
|
||||
sign=0
|
||||
#1:AES128, 2:AES256, 3:AES192
|
||||
encrypt_type=0
|
||||
key_sel=0
|
||||
#0:AES CTR MODE, 1:AES XTS MODE
|
||||
xts_mode=0
|
||||
aes_region_lock=0
|
||||
no_segment=1
|
||||
boot2_enable=0
|
||||
boot2_rollback=0
|
||||
cpu_master_id=0
|
||||
notload_in_bootrom=0
|
||||
crc_ignore=1
|
||||
hash_ignore=1
|
||||
power_on_mm=1
|
||||
em_sel=1
|
||||
cmds_en=1
|
||||
#0:cmds bypass wrap commands to macro, original mode;
|
||||
#1:cmds handle wrap commands, original mode;
|
||||
#2:cmds bypass wrap commands to macro, cmds force wrap16*4 splitted into two wrap8*4;
|
||||
#3:cmds handle wrap commands, cmds force wrap16*4 splitted into two wrap8*4
|
||||
cmds_wrap_mode=2
|
||||
#0:SF_CTRL_WRAP_LEN_8, 1:SF_CTRL_WRAP_LEN_16, 2:SF_CTRL_WRAP_LEN_32,
|
||||
#3:SF_CTRL_WRAP_LEN_64, 9: SF_CTRL_WRAP_LEN_4096
|
||||
cmds_wrap_len=2
|
||||
icache_invalid=1
|
||||
dcache_invalid=1
|
||||
fpga_halt_release=0
|
||||
|
||||
########################image cfg####################################
|
||||
#flash controller offset
|
||||
group_image_offset=0x00002000
|
||||
aes_region_len=0
|
||||
|
||||
#total image len or segment count
|
||||
img_len_cnt=0x8000
|
||||
#img hash
|
||||
hash_0=0xdeadbeef
|
||||
hash_1=0
|
||||
hash_2=0
|
||||
hash_3=0
|
||||
hash_4=0
|
||||
hash_5=0
|
||||
hash_6=0
|
||||
hash_7=0
|
||||
|
||||
########################CPU M0 cfg###################################
|
||||
m0_config_enable=1
|
||||
m0_halt_cpu=0
|
||||
m0_cache_enable=0
|
||||
m0_cache_wa=0
|
||||
m0_cache_wb=0
|
||||
m0_cache_wt=0
|
||||
m0_cache_way_dis=0
|
||||
m0_reserved=0
|
||||
m0_cache_range_h=0
|
||||
m0_cache_range_l=0
|
||||
|
||||
#img RAM address or flash offset
|
||||
m0_image_address_offset=0x00002000
|
||||
m0_boot_entry=0x58000000
|
||||
m0_msp_val=0
|
||||
|
||||
########################CPU D0 cfg###################################
|
||||
d0_config_enable=1
|
||||
d0_halt_cpu=0
|
||||
d0_cache_enable=0
|
||||
d0_cache_wa=0
|
||||
d0_cache_wb=0
|
||||
d0_cache_wt=0
|
||||
d0_cache_way_dis=0
|
||||
d0_reserved=0
|
||||
d0_cache_range_h=0
|
||||
d0_cache_range_l=0
|
||||
|
||||
#img RAM address or flash offset
|
||||
d0_image_address_offset=0x00022000
|
||||
d0_boot_entry=0x58020000
|
||||
d0_msp_val=0
|
||||
|
||||
########################CPU LP cfg###################################
|
||||
lp_config_enable=1
|
||||
lp_halt_cpu=0
|
||||
lp_cache_enable=0
|
||||
lp_cache_wa=0
|
||||
lp_cache_wb=0
|
||||
lp_cache_wt=0
|
||||
lp_cache_way_dis=0
|
||||
lp_reserved=0
|
||||
lp_cache_range_h=0x58050000
|
||||
lp_cache_range_l=0x58040000
|
||||
|
||||
#img RAM address or flash offset
|
||||
lp_image_address_offset=0x00042000
|
||||
lp_boot_entry=0x58040000
|
||||
lp_msp_val=0
|
||||
|
||||
boot2_pt_table_0=0
|
||||
boot2_pt_table_1=0
|
||||
|
||||
flashCfgTableAddr=0
|
||||
flashCfgTableLen=0
|
||||
|
||||
########################patch on read################################
|
||||
patch_read_addr0=0
|
||||
patch_read_value0=0
|
||||
patch_read_addr1=0
|
||||
patch_read_value1=0
|
||||
patch_read_addr2=0
|
||||
patch_read_value2=0
|
||||
patch_read_addr3=0
|
||||
patch_read_value3=0
|
||||
|
||||
########################patch on jump################################
|
||||
patch_jump_addr0=0x20000320
|
||||
patch_jump_value0=0
|
||||
patch_jump_addr1=0
|
||||
patch_jump_value1=0
|
||||
patch_jump_addr2=0
|
||||
patch_jump_value2=0
|
||||
patch_jump_addr3=0
|
||||
patch_jump_value3=0
|
||||
|
||||
reserved1=0
|
||||
reserved2=0
|
||||
reserved3=0
|
||||
reserved4=0
|
||||
|
||||
crc32=0xdeadbeef
|
||||
|
||||
[BOOTHEADER_GROUP1_CFG]
|
||||
magic_code=0x50414642
|
||||
revision=1
|
||||
|
||||
#########################flash cfg(ignored for group1)###############
|
||||
#########################clk cfg(ignored for group1)#################
|
||||
########################boot cfg#####################################
|
||||
#1:ECC
|
||||
sign=0
|
||||
#1:AES128,2:AES256,3:AES192
|
||||
encrypt_type=0
|
||||
key_sel=0
|
||||
xts_mode=0
|
||||
aes_region_lock=0
|
||||
no_segment=1
|
||||
boot2_enable=0
|
||||
boot2_rollback=0
|
||||
cpu_master_id=0
|
||||
notload_in_bootrom=0
|
||||
crc_ignore=1
|
||||
hash_ignore=1
|
||||
power_on_mm=0
|
||||
em_sel=0
|
||||
cmds_en=1
|
||||
cmds_wrap_mode=2
|
||||
#2:SF_CTRL_WRAP_LEN_32, 3:SF_CTRL_WRAP_LEN_64, 9: SF_CTRL_WRAP_LEN_4096
|
||||
cmds_wrap_len=2
|
||||
icache_invalid=1
|
||||
dcache_invalid=1
|
||||
fpga_halt_release=0
|
||||
|
||||
########################image cfg####################################
|
||||
#flash controller offset
|
||||
group_image_offset=0x00052000
|
||||
aes_region_len=0
|
||||
|
||||
#total image len or segment count
|
||||
img_len_cnt=0x8000
|
||||
#img hash
|
||||
hash_0=0xdeadbeef
|
||||
hash_1=0
|
||||
hash_2=0
|
||||
hash_3=0
|
||||
hash_4=0
|
||||
hash_5=0
|
||||
hash_6=0
|
||||
hash_7=0
|
||||
|
||||
########################CPU M0 cfg###################################
|
||||
m0_config_enable=1
|
||||
m0_halt_cpu=0
|
||||
m0_cache_enable=0
|
||||
m0_cache_wa=0
|
||||
m0_cache_wb=0
|
||||
m0_cache_wt=0
|
||||
m0_cache_way_dis=0
|
||||
m0_reserved=0
|
||||
m0_cache_range_h=0
|
||||
m0_cache_range_l=0
|
||||
|
||||
#img RAM address or flash offset
|
||||
m0_image_address_offset=0x00052000
|
||||
m0_boot_entry=0xD8000000
|
||||
m0_msp_val=0
|
||||
|
||||
########################CPU D0 cfg###################################
|
||||
d0_config_enable=1
|
||||
d0_halt_cpu=0
|
||||
d0_cache_enable=0
|
||||
d0_cache_wa=0
|
||||
d0_cache_wb=0
|
||||
d0_cache_wt=0
|
||||
d0_cache_way_dis=0
|
||||
d0_reserved=0
|
||||
d0_cache_range_h=0
|
||||
d0_cache_range_l=0
|
||||
|
||||
#img RAM address or flash offset
|
||||
d0_image_address_offset=0x00072000
|
||||
d0_boot_entry=0x58020000
|
||||
d0_msp_val=0
|
||||
|
||||
########################CPU LP cfg###################################
|
||||
lp_config_enable=1
|
||||
lp_halt_cpu=0
|
||||
lp_cache_enable=0
|
||||
lp_cache_wa=0
|
||||
lp_cache_wb=0
|
||||
lp_cache_wt=0
|
||||
lp_cache_way_dis=0
|
||||
lp_reserved=0
|
||||
lp_cache_range_h=0
|
||||
lp_cache_range_l=0
|
||||
|
||||
#img RAM address or flash offset
|
||||
lp_image_address_offset=0x00082000
|
||||
lp_boot_entry=0x58040000
|
||||
lp_msp_val=0
|
||||
|
||||
boot2_pt_table_0=0
|
||||
boot2_pt_table_1=0
|
||||
|
||||
flashCfgTableAddr=0
|
||||
flashCfgTableLen=0
|
||||
|
||||
########################patch on read################################
|
||||
patch_read_addr0=0
|
||||
patch_read_value0=0
|
||||
patch_read_addr1=0
|
||||
patch_read_value1=0
|
||||
patch_read_addr2=0
|
||||
patch_read_value2=0
|
||||
patch_read_addr3=0
|
||||
patch_read_value3=0
|
||||
|
||||
########################patch on jump################################
|
||||
patch_jump_addr0=0x20000320
|
||||
patch_jump_value0=0
|
||||
patch_jump_addr1=0
|
||||
patch_jump_value1=0
|
||||
patch_jump_addr2=0
|
||||
patch_jump_value2=0
|
||||
patch_jump_addr3=0
|
||||
patch_jump_value3=0
|
||||
|
||||
reserved1=0
|
||||
reserved2=0
|
||||
reserved3=0
|
||||
reserved4=0
|
||||
|
||||
crc32=0xdeadbeef
|
||||
119
chips/bl616/eflash_loader/eflash_loader_cfg.conf
Normal file
119
chips/bl616/eflash_loader/eflash_loader_cfg.conf
Normal file
|
|
@ -0,0 +1,119 @@
|
|||
[LOAD_CFG]
|
||||
#jlink or uart
|
||||
interface = uart
|
||||
device = COM1
|
||||
speed_uart_boot = 500000
|
||||
speed_uart_load = 2000000
|
||||
#cklink usb vid|pid
|
||||
cklink_vidpid = 42bf|b210
|
||||
cklink_type = CKLink_Lite_Vendor-rog
|
||||
#eg: rv_dbg_plus, ft2232hl, ft2232d
|
||||
openocd_config = rv_dbg_plus
|
||||
auto_burn = false
|
||||
speed_jlink = 1000
|
||||
#0:without load, 1:eflash_loader load, 2: bootrom load
|
||||
load_function = 2
|
||||
do_reset = true
|
||||
#reset retry+hold time
|
||||
reset_hold_time = 50
|
||||
shake_hand_delay = 100
|
||||
reset_revert = false
|
||||
cutoff_time = 50
|
||||
shake_hand_retry = 3
|
||||
flash_burn_retry = 1
|
||||
checksum_err_retry = 3
|
||||
erase_time_out = 100000
|
||||
#chiptype=bl616
|
||||
check_mac = true
|
||||
#0:no erase,1:programmed section erase,2:chip erase
|
||||
erase = 1
|
||||
# switch eflash_loader command log save
|
||||
local_log = false
|
||||
#0:verify by calculating SHA256(xip), >0:read back verify and verify by calculating SHA256(sbus)
|
||||
verify = 0
|
||||
tx_size = 2056
|
||||
cpu_reset_after_load = false
|
||||
#empty for auto, otherwise specified clock para file path: eg: chips/bl616/efuse_bootheader/clock_para.bin
|
||||
clock_para = ""
|
||||
#skip mode set first para is skip addr, second para is skip len
|
||||
skip_mode = 0x0, 0x0
|
||||
boot2_isp_mode = 0
|
||||
isp_mode_speed = 2000000
|
||||
isp_shakehand_timeout = 0
|
||||
|
||||
[FLASH_CFG]
|
||||
flash_id = ef4016
|
||||
#bit 7-4 flash_clock_type: 0:120M wifipll, 1:xtal, 2:128M cpupll, 3:80M wifipll, 4:bclk, 5:96M wifipll
|
||||
#bit 3-0 flash_clock_div
|
||||
flash_clock_cfg = 0x41
|
||||
#0:0.5T delay, 1:1T delay, 2:1.5T delay, 3:2T delay
|
||||
flash_clock_delay = 0
|
||||
#0:NIO, 1:DO, 2:QO, 3:DIO, 4:QIO
|
||||
flash_io_mode = 1
|
||||
#flash_pin value:
|
||||
#bit 7 flash pin autoscan
|
||||
#bit 6 flash select 0: flash1, 1: flash2
|
||||
#bit 5-0 flash pin cfg:
|
||||
#0x0: single flash, sf1 internal swap io3 and io0
|
||||
#0x1: single flash, sf1 internal swap io3 with io0 and io2 with cs
|
||||
#0x2: single flash, sf1 internal no swap
|
||||
#0x3: single flash, sf1 internal swap io2 with cs
|
||||
#0x4: single flash, sf2 external GPIO4-9 and swap io3 with io0
|
||||
#0x8: single flash, sf3 external GPIO10-15
|
||||
#0x14:dual flash, sf1 internal swap io3 and io0, sf2 external GPIO4-9 swap io3 with io0
|
||||
#0x15:dual flash, sf1 internal swap io3 with io0 and io2 with cs, sf2 external GPIO4-9 swap io3 with io0
|
||||
#0x16:dual flash, sf1 internal no swap, sf2 external GPIO4-9 swap io3 with io0
|
||||
#0x17:dual flash, sf1 internal swap io2 with cs, sf2 external GPIO4-9 swap io3 with io0
|
||||
#0x24:single flash, sf2 external GPIO4-9
|
||||
#0x34:dual flash, sf1 internal swap io3 and io0, sf2 external GPIO4-9 no swap
|
||||
#0x35:dual flash, sf1 internal swap io3 with io0 and io2 with cs, sf2 external GPIO4-9 no swap
|
||||
#0x36:dual flash, sf1 internal no swap, sf2 external GPIO4-9 no swap
|
||||
#0x37:dual flash, sf1 internal swap io2 with cs, sf2 external GPIO4-9 no swap
|
||||
flash_pin = 0x80
|
||||
#empty for auto, otherwise specified flash para file path: eg: chips/bl616/efuse_bootheader/flash_para.bin
|
||||
flash_para = chips/bl616/efuse_bootheader/flash_para.bin
|
||||
decompress_write = false
|
||||
file = chips/bl616/img_create2/whole_img.bin
|
||||
address = 00000000
|
||||
|
||||
[FLASH2_CFG]
|
||||
flash2_en = false
|
||||
#flash size, 0:0.5M, 1:1M, 2:2M, 4: 4M, 8: 8M, 16: 16M
|
||||
flash1_size = 4
|
||||
flash2_size = 2
|
||||
flash2_id = ef4015
|
||||
flash2_clock_cfg = 0x41
|
||||
#0:0.5T delay, 1:1T delay, 2:1.5T delay, 3:2T delay
|
||||
flash2_clock_delay = 0
|
||||
#0:NIO, 1:DO, 2:QO, 3:DIO, 4:QIO
|
||||
flash2_io_mode = 0x10
|
||||
#flash_pin value:
|
||||
#bit 7 flash pin autoscan
|
||||
#bit 6 flash select 0: flash1, 1: flash2
|
||||
#bit 5-0 flash pin cfg:
|
||||
#0x0: single flash, sf1 internal swap io3 and io0
|
||||
#0x1: single flash, sf1 internal swap io3 with io0 and io2 with cs
|
||||
#0x2: single flash, sf1 internal no swap
|
||||
#0x3: single flash, sf1 internal swap io2 with cs
|
||||
#0x4: single flash, sf2 external GPIO4-9 and swap io3 with io0
|
||||
#0x8: single flash, sf3 external GPIO10-15
|
||||
#0x14:dual flash, sf1 internal swap io3 and io0, sf2 external GPIO4-9 swap io3 with io0
|
||||
#0x15:dual flash, sf1 internal swap io3 with io0 and io2 with cs, sf2 external GPIO4-9 swap io3 with io0
|
||||
#0x16:dual flash, sf1 internal no swap, sf2 external GPIO4-9 swap io3 with io0
|
||||
#0x17:dual flash, sf1 internal swap io2 with cs, sf2 external GPIO4-9 swap io3 with io0
|
||||
#0x24:single flash, sf2 external GPIO4-9
|
||||
#0x34:dual flash, sf1 internal swap io3 and io0, sf2 external GPIO4-9 no swap
|
||||
#0x35:dual flash, sf1 internal swap io3 with io0 and io2 with cs, sf2 external GPIO4-9 no swap
|
||||
#0x36:dual flash, sf1 internal no swap, sf2 external GPIO4-9 no swap
|
||||
#0x37:dual flash, sf1 internal swap io2 with cs, sf2 external GPIO4-9 no swap
|
||||
flash2_pin = 0xC0
|
||||
#empty for auto, otherwise specified flash para file path: eg: chips/bl616/efuse_bootheader/flash2_para.bin
|
||||
flash2_para = chips/bl616/efuse_bootheader/flash2_para.bin
|
||||
|
||||
[EFUSE_CFG]
|
||||
burn_en = true
|
||||
factory_mode = false
|
||||
security_write = false
|
||||
security_save = true
|
||||
file = ../../../Tools/img_tools/efuse_bootheader/efusedata.bin
|
||||
maskfile = ../../../Tools/img_tools/efuse_bootheader/efusedata_mask.bin
|
||||
119
chips/bl616/eflash_loader/eflash_loader_cfg.ini
Normal file
119
chips/bl616/eflash_loader/eflash_loader_cfg.ini
Normal file
|
|
@ -0,0 +1,119 @@
|
|||
[LOAD_CFG]
|
||||
#jlink or uart
|
||||
interface = uart
|
||||
device = COM1
|
||||
speed_uart_boot = 500000
|
||||
speed_uart_load = 2000000
|
||||
#cklink usb vid|pid
|
||||
cklink_vidpid = 42bf|b210
|
||||
cklink_type = CKLink_Lite_Vendor-rog
|
||||
#eg: rv_dbg_plus, ft2232hl, ft2232d
|
||||
openocd_config = rv_dbg_plus
|
||||
auto_burn = false
|
||||
speed_jlink = 1000
|
||||
#0:without load, 1:eflash_loader load, 2: bootrom load
|
||||
load_function = 2
|
||||
do_reset = true
|
||||
#reset retry+hold time
|
||||
reset_hold_time = 50
|
||||
shake_hand_delay = 100
|
||||
reset_revert = false
|
||||
cutoff_time = 50
|
||||
shake_hand_retry = 3
|
||||
flash_burn_retry = 1
|
||||
checksum_err_retry = 3
|
||||
erase_time_out = 100000
|
||||
#chiptype=bl616
|
||||
check_mac = true
|
||||
#0:no erase,1:programmed section erase,2:chip erase
|
||||
erase = 1
|
||||
# switch eflash_loader command log save
|
||||
local_log = false
|
||||
#0:verify by calculating SHA256(xip), >0:read back verify and verify by calculating SHA256(sbus)
|
||||
verify = 0
|
||||
tx_size = 2056
|
||||
cpu_reset_after_load = false
|
||||
#empty for auto, otherwise specified clock para file path: eg: chips/bl616/efuse_bootheader/clock_para.bin
|
||||
clock_para =
|
||||
#skip mode set first para is skip addr, second para is skip len
|
||||
skip_mode = 0x0, 0x0
|
||||
boot2_isp_mode = 0
|
||||
isp_mode_speed = 2000000
|
||||
isp_shakehand_timeout = 0
|
||||
|
||||
[FLASH_CFG]
|
||||
flash_id = ef4016
|
||||
#bit 7-4 flash_clock_type: 0:120M wifipll, 1:xtal, 2:128M cpupll, 3:80M wifipll, 4:bclk, 5:96M wifipll
|
||||
#bit 3-0 flash_clock_div
|
||||
flash_clock_cfg = 0x41
|
||||
#0:0.5T delay, 1:1T delay, 2:1.5T delay, 3:2T delay
|
||||
flash_clock_delay = 0
|
||||
#0:NIO, 1:DO, 2:QO, 3:DIO, 4:QIO
|
||||
flash_io_mode = 1
|
||||
#flash_pin value:
|
||||
#bit 7 flash pin autoscan
|
||||
#bit 6 flash select 0: flash1, 1: flash2
|
||||
#bit 5-0 flash pin cfg:
|
||||
#0x0: single flash, sf1 internal swap io3 and io0
|
||||
#0x1: single flash, sf1 internal swap io3 with io0 and io2 with cs
|
||||
#0x2: single flash, sf1 internal no swap
|
||||
#0x3: single flash, sf1 internal swap io2 with cs
|
||||
#0x4: single flash, sf2 external GPIO4-9 and swap io3 with io0
|
||||
#0x8: single flash, sf3 external GPIO10-15
|
||||
#0x14:dual flash, sf1 internal swap io3 and io0, sf2 external GPIO4-9 swap io3 with io0
|
||||
#0x15:dual flash, sf1 internal swap io3 with io0 and io2 with cs, sf2 external GPIO4-9 swap io3 with io0
|
||||
#0x16:dual flash, sf1 internal no swap, sf2 external GPIO4-9 swap io3 with io0
|
||||
#0x17:dual flash, sf1 internal swap io2 with cs, sf2 external GPIO4-9 swap io3 with io0
|
||||
#0x24:single flash, sf2 external GPIO4-9
|
||||
#0x34:dual flash, sf1 internal swap io3 and io0, sf2 external GPIO4-9 no swap
|
||||
#0x35:dual flash, sf1 internal swap io3 with io0 and io2 with cs, sf2 external GPIO4-9 no swap
|
||||
#0x36:dual flash, sf1 internal no swap, sf2 external GPIO4-9 no swap
|
||||
#0x37:dual flash, sf1 internal swap io2 with cs, sf2 external GPIO4-9 no swap
|
||||
flash_pin = 0x80
|
||||
#empty for auto, otherwise specified flash para file path: eg: chips/bl616/efuse_bootheader/flash_para.bin
|
||||
flash_para = chips/bl616/efuse_bootheader/flash_para.bin
|
||||
decompress_write = false
|
||||
file = chips/bl616/img_create/usbd_cdc_acm_bl616.bin
|
||||
address = 000000
|
||||
|
||||
[FLASH2_CFG]
|
||||
flash2_en = false
|
||||
#flash size, 0:0.5M, 1:1M, 2:2M, 4: 4M, 8: 8M, 16: 16M
|
||||
flash1_size = 4
|
||||
flash2_size = 2
|
||||
flash2_id = ef4015
|
||||
flash2_clock_cfg = 0x41
|
||||
#0:0.5T delay, 1:1T delay, 2:1.5T delay, 3:2T delay
|
||||
flash2_clock_delay = 0
|
||||
#0:NIO, 1:DO, 2:QO, 3:DIO, 4:QIO
|
||||
flash2_io_mode = 0x10
|
||||
#flash_pin value:
|
||||
#bit 7 flash pin autoscan
|
||||
#bit 6 flash select 0: flash1, 1: flash2
|
||||
#bit 5-0 flash pin cfg:
|
||||
#0x0: single flash, sf1 internal swap io3 and io0
|
||||
#0x1: single flash, sf1 internal swap io3 with io0 and io2 with cs
|
||||
#0x2: single flash, sf1 internal no swap
|
||||
#0x3: single flash, sf1 internal swap io2 with cs
|
||||
#0x4: single flash, sf2 external GPIO4-9 and swap io3 with io0
|
||||
#0x8: single flash, sf3 external GPIO10-15
|
||||
#0x14:dual flash, sf1 internal swap io3 and io0, sf2 external GPIO4-9 swap io3 with io0
|
||||
#0x15:dual flash, sf1 internal swap io3 with io0 and io2 with cs, sf2 external GPIO4-9 swap io3 with io0
|
||||
#0x16:dual flash, sf1 internal no swap, sf2 external GPIO4-9 swap io3 with io0
|
||||
#0x17:dual flash, sf1 internal swap io2 with cs, sf2 external GPIO4-9 swap io3 with io0
|
||||
#0x24:single flash, sf2 external GPIO4-9
|
||||
#0x34:dual flash, sf1 internal swap io3 and io0, sf2 external GPIO4-9 no swap
|
||||
#0x35:dual flash, sf1 internal swap io3 with io0 and io2 with cs, sf2 external GPIO4-9 no swap
|
||||
#0x36:dual flash, sf1 internal no swap, sf2 external GPIO4-9 no swap
|
||||
#0x37:dual flash, sf1 internal swap io2 with cs, sf2 external GPIO4-9 no swap
|
||||
flash2_pin = 0xC0
|
||||
#empty for auto, otherwise specified flash para file path: eg: chips/bl616/efuse_bootheader/flash2_para.bin
|
||||
flash2_para = chips/bl616/efuse_bootheader/flash2_para.bin
|
||||
|
||||
[EFUSE_CFG]
|
||||
burn_en = true
|
||||
factory_mode = false
|
||||
security_write = false
|
||||
security_save = true
|
||||
file = ../../../Tools/img_tools/efuse_bootheader/efusedata.bin
|
||||
maskfile = ../../../Tools/img_tools/efuse_bootheader/efusedata_mask.bin
|
||||
382
chips/bl616/efuse_bootheader/efuse_bootheader_cfg.conf
Normal file
382
chips/bl616/efuse_bootheader/efuse_bootheader_cfg.conf
Normal file
|
|
@ -0,0 +1,382 @@
|
|||
[EFUSE_CFG]
|
||||
########################################################################
|
||||
ef_sf_aes_mode = 0
|
||||
ef_sboot_en = 0
|
||||
ef_dbg_jtag_0_dis = 0
|
||||
ef_dbg_mode = 0
|
||||
###################################################################
|
||||
ef_dbg_pwd_low = 0
|
||||
ef_dbg_pwd_high = 0
|
||||
##########################################
|
||||
sign_cfg = 0
|
||||
################################################################
|
||||
|
||||
ef_key_slot_0_w0 = 0
|
||||
ef_key_slot_0_w1 = 0
|
||||
ef_key_slot_0_w2 = 0
|
||||
ef_key_slot_0_w3 = 0
|
||||
ef_key_slot_1_w0 = 0
|
||||
ef_key_slot_1_w1 = 0
|
||||
ef_key_slot_1_w2 = 0
|
||||
ef_key_slot_1_w3 = 0
|
||||
ef_key_slot_2_w0 = 0
|
||||
ef_key_slot_2_w1 = 0
|
||||
ef_key_slot_2_w2 = 0
|
||||
ef_key_slot_2_w3 = 0
|
||||
ef_key_slot_3_w0 = 0
|
||||
ef_key_slot_3_w1 = 0
|
||||
ef_key_slot_3_w2 = 0
|
||||
ef_key_slot_3_w3 = 0
|
||||
wr_lock_key_slot_0 = 0
|
||||
wr_lock_key_slot_1 = 0
|
||||
wr_lock_key_slot_2 = 0
|
||||
wr_lock_key_slot_3 = 0
|
||||
wr_lock_sw_usage_0 = 0
|
||||
wr_lock_sw_usage_1 = 0
|
||||
wr_lock_sw_usage_2 = 0
|
||||
wr_lock_sw_usage_3 = 0
|
||||
wr_lock_key_slot_11 = 0
|
||||
rd_lock_dbg_pwd = 0
|
||||
rd_lock_key_slot_0 = 0
|
||||
rd_lock_key_slot_1 = 0
|
||||
rd_lock_key_slot_2 = 0
|
||||
rd_lock_key_slot_3 = 0
|
||||
rd_lock_key_slot_11 = 0
|
||||
########################################################################
|
||||
ef_key_slot_4_w0 = 0
|
||||
ef_key_slot_4_w1 = 0
|
||||
ef_key_slot_4_w2 = 0
|
||||
ef_key_slot_4_w3 = 0
|
||||
ef_key_slot_5_w0 = 0
|
||||
ef_key_slot_5_w1 = 0
|
||||
ef_key_slot_5_w2 = 0
|
||||
ef_key_slot_5_w3 = 0
|
||||
ef_key_slot_6_w0 = 0
|
||||
ef_key_slot_6_w1 = 0
|
||||
ef_key_slot_6_w2 = 0
|
||||
ef_key_slot_6_w3 = 0
|
||||
ef_key_slot_7_w0 = 0
|
||||
ef_key_slot_7_w1 = 0
|
||||
ef_key_slot_7_w2 = 0
|
||||
ef_key_slot_7_w3 = 0
|
||||
ef_key_slot_8_w0 = 0
|
||||
ef_key_slot_8_w1 = 0
|
||||
ef_key_slot_8_w2 = 0
|
||||
ef_key_slot_8_w3 = 0
|
||||
ef_key_slot_9_w0 = 0
|
||||
ef_key_slot_9_w1 = 0
|
||||
ef_key_slot_9_w2 = 0
|
||||
ef_key_slot_9_w3 = 0
|
||||
ef_key_slot_10_w0 = 0
|
||||
ef_key_slot_10_w1 = 0
|
||||
ef_key_slot_10_w2 = 0
|
||||
ef_key_slot_10_w3 = 0
|
||||
ef_dat_1_rsvd_0 = 0
|
||||
ef_dat_1_rsvd_1 = 0
|
||||
ef_dat_1_rsvd_2 = 0
|
||||
########################################################################
|
||||
wr_lock_rsvd_2 = 0
|
||||
wr_lock_key_slot_4 = 0
|
||||
wr_lock_key_slot_5 = 0
|
||||
wr_lock_key_slot_6 = 0
|
||||
wr_lock_key_slot_7 = 0
|
||||
wr_lock_key_slot_8 = 0
|
||||
wr_lock_key_slot_9 = 0
|
||||
wr_lock_key_slot_10 = 0
|
||||
wr_lock_dat_1_rsvd_0 = 0
|
||||
wr_lock_dat_1_rsvd_1 = 0
|
||||
wr_lock_dat_1_rsvd_2 = 0
|
||||
rd_lock_key_slot_4 = 0
|
||||
rd_lock_key_slot_5 = 0
|
||||
rd_lock_key_slot_6 = 0
|
||||
rd_lock_key_slot_7 = 0
|
||||
rd_lock_key_slot_8 = 0
|
||||
rd_lock_key_slot_9 = 0
|
||||
rd_lock_key_slot_10 = 0
|
||||
########################################################################
|
||||
ef_zone_00_w0 = 0
|
||||
ef_zone_00_w1 = 0
|
||||
ef_zone_00_w2 = 0
|
||||
ef_zone_00_w3 = 0
|
||||
ef_zone_01_w0 = 0
|
||||
ef_zone_01_w1 = 0
|
||||
ef_zone_01_w2 = 0
|
||||
ef_zone_01_w3 = 0
|
||||
ef_zone_02_w0 = 0
|
||||
ef_zone_02_w1 = 0
|
||||
ef_zone_02_w2 = 0
|
||||
ef_zone_02_w3 = 0
|
||||
ef_zone_03_w0 = 0
|
||||
ef_zone_03_w1 = 0
|
||||
ef_zone_03_w2 = 0
|
||||
ef_zone_03_w3 = 0
|
||||
ef_zone_04_w0 = 0
|
||||
ef_zone_04_w1 = 0
|
||||
ef_zone_04_w2 = 0
|
||||
ef_zone_04_w3 = 0
|
||||
ef_zone_05_w0 = 0
|
||||
ef_zone_05_w1 = 0
|
||||
ef_zone_05_w2 = 0
|
||||
ef_zone_05_w3 = 0
|
||||
ef_zone_06_w0 = 0
|
||||
ef_zone_06_w1 = 0
|
||||
ef_zone_06_w2 = 0
|
||||
ef_zone_06_w3 = 0
|
||||
ef_zone_07_w0 = 0
|
||||
ef_zone_07_w1 = 0
|
||||
ef_zone_07_w2 = 0
|
||||
ef_zone_07_w3 = 0
|
||||
ef_zone_08_w0 = 0
|
||||
ef_zone_08_w1 = 0
|
||||
ef_zone_08_w2 = 0
|
||||
ef_zone_08_w3 = 0
|
||||
ef_zone_09_w0 = 0
|
||||
ef_zone_09_w1 = 0
|
||||
ef_zone_09_w2 = 0
|
||||
ef_zone_09_w3 = 0
|
||||
ef_zone_10_w0 = 0
|
||||
ef_zone_10_w1 = 0
|
||||
ef_zone_10_w2 = 0
|
||||
ef_zone_10_w3 = 0
|
||||
ef_zone_11_w0 = 0
|
||||
ef_zone_11_w1 = 0
|
||||
ef_zone_11_w2 = 0
|
||||
ef_zone_11_w3 = 0
|
||||
ef_zone_12_w0 = 0
|
||||
ef_zone_12_w1 = 0
|
||||
ef_zone_12_w2 = 0
|
||||
ef_zone_12_w3 = 0
|
||||
ef_zone_13_w0 = 0
|
||||
ef_zone_13_w1 = 0
|
||||
ef_zone_13_w2 = 0
|
||||
ef_zone_13_w3 = 0
|
||||
ef_zone_14_w0 = 0
|
||||
ef_zone_14_w1 = 0
|
||||
ef_zone_14_w2 = 0
|
||||
ef_zone_14_w3 = 0
|
||||
ef_zone_15_w0 = 0
|
||||
ef_zone_15_w1 = 0
|
||||
ef_zone_15_w2 = 0
|
||||
ef_zone_15_w3 = 0
|
||||
|
||||
[BOOTHEADER_GROUP0_CFG]
|
||||
magic_code = 0x504e4642
|
||||
revision = 0x01
|
||||
#########################flash cfg#############################
|
||||
flashcfg_magic_code = 0x47464346
|
||||
#flashcfg_magic_code=0
|
||||
io_mode = 0x10
|
||||
#0.5T sfctrl_clk_delay=0 sfctrl_clk_invert=3
|
||||
#1 T sfctrl_clk_delay=1 sfctrl_clk_invert=1
|
||||
#1.5T sfctrl_clk_delay=1 sfctrl_clk_invert=3
|
||||
cont_read_support = 0
|
||||
sfctrl_clk_delay = 1
|
||||
sfctrl_clk_invert = 0x01
|
||||
|
||||
reset_en_cmd = 0x66
|
||||
reset_cmd = 0x99
|
||||
exit_contread_cmd = 0xff
|
||||
exit_contread_cmd_size = 0x3
|
||||
|
||||
jedecid_cmd = 0x9f
|
||||
jedecid_cmd_dmy_clk = 0
|
||||
enter_32bits_addr_cmd = 0xb7
|
||||
exit_32bits_addr_clk = 0xe9
|
||||
|
||||
sector_size = 4
|
||||
mfg_id = 0xff
|
||||
page_size = 256
|
||||
|
||||
chip_erase_cmd = 0xc7
|
||||
sector_erase_cmd = 0x20
|
||||
blk32k_erase_cmd = 0x52
|
||||
blk64k_erase_cmd = 0xd8
|
||||
|
||||
write_enable_cmd = 0x06
|
||||
page_prog_cmd = 0x02
|
||||
qpage_prog_cmd = 0x32
|
||||
qual_page_prog_addr_mode = 0
|
||||
|
||||
fast_read_cmd = 0x0b
|
||||
fast_read_dmy_clk = 1
|
||||
qpi_fast_read_cmd = 0x0b
|
||||
qpi_fast_read_dmy_clk = 1
|
||||
|
||||
fast_read_do_cmd = 0x3b
|
||||
fast_read_do_dmy_clk = 1
|
||||
fast_read_dio_cmd = 0xbb
|
||||
fast_read_dio_dmy_clk = 0
|
||||
|
||||
fast_read_qo_cmd = 0x6b
|
||||
fast_read_qo_dmy_clk = 1
|
||||
fast_read_qio_cmd = 0xeb
|
||||
fast_read_qio_dmy_clk = 2
|
||||
|
||||
qpi_fast_read_qio_cmd = 0xeb
|
||||
qpi_fast_read_qio_dmy_clk = 2
|
||||
qpi_page_prog_cmd = 0x02
|
||||
write_vreg_enable_cmd = 0x50
|
||||
|
||||
wel_reg_index = 0
|
||||
qe_reg_index = 1
|
||||
busy_reg_index = 0
|
||||
wel_bit_pos = 1
|
||||
|
||||
qe_bit_pos = 1
|
||||
busy_bit_pos = 0
|
||||
wel_reg_write_len = 2
|
||||
wel_reg_read_len = 1
|
||||
|
||||
qe_reg_write_len = 2
|
||||
qe_reg_read_len = 1
|
||||
release_power_down = 0xab
|
||||
busy_reg_read_len = 1
|
||||
|
||||
reg_read_cmd0 = 0x05
|
||||
reg_read_cmd1 = 0x35
|
||||
|
||||
reg_write_cmd0 = 0x01
|
||||
reg_write_cmd1 = 0x01
|
||||
|
||||
enter_qpi_cmd = 0x38
|
||||
exit_qpi_cmd = 0xff
|
||||
cont_read_code = 0x20
|
||||
cont_read_exit_code = 0xf0
|
||||
|
||||
burst_wrap_cmd = 0x77
|
||||
burst_wrap_dmy_clk = 0x03
|
||||
burst_wrap_data_mode = 2
|
||||
burst_wrap_code = 0x40
|
||||
|
||||
de_burst_wrap_cmd = 0x77
|
||||
de_burst_wrap_cmd_dmy_clk = 0x03
|
||||
de_burst_wrap_code_mode = 2
|
||||
de_burst_wrap_code = 0xf0
|
||||
|
||||
sector_erase_time = 300
|
||||
blk32k_erase_time = 1200
|
||||
|
||||
blk64k_erase_time = 1200
|
||||
|
||||
page_prog_time = 50
|
||||
|
||||
chip_erase_time = 200000
|
||||
power_down_delay = 20
|
||||
qe_data = 0
|
||||
|
||||
flashcfg_crc32 = 0
|
||||
|
||||
#########################clk cfg#####################################
|
||||
clkcfg_magic_code = 0x47464350
|
||||
#clkcfg_magic_code=0
|
||||
|
||||
#0:None,1:24M,2:32M,3:38.4M,4:40M,5:26M,6:RC32M
|
||||
xtal_type = 7
|
||||
#mcu_clk 0:RC32M;1:XTAL;2:aupll_div2;3:aupll_div1;4:wifipll_240M;5:wifipll_320M
|
||||
mcu_clk = 5
|
||||
mcu_clk_div = 0
|
||||
mcu_bclk_div = 0
|
||||
mcu_pbclk_div = 3
|
||||
|
||||
#0:mcu pbclk,1:cpupll 200M,2:wifipll 320M,3:cpupll 400M
|
||||
emi_clk = 2
|
||||
emi_clk_div = 1
|
||||
|
||||
#flash_clk_type 0:wifipll_120M;1:xtal;2:aupll_div5;3:muxpll_80M;4:bclk;5:wifipll_96M
|
||||
flash_clk_type = 1
|
||||
flash_clk_div = 0
|
||||
|
||||
wifipll_pu = 1
|
||||
aupll_pu = 1
|
||||
|
||||
rsvd0 = 0
|
||||
|
||||
clkcfg_crc32 = 0
|
||||
|
||||
########################boot cfg#####################################
|
||||
#1:ECC
|
||||
sign = 0
|
||||
#1:AES128 CTR,2:AES256 CTR,3:AES192 CTR,4:AES128 XTS
|
||||
encrypt_type = 0
|
||||
key_sel = 0
|
||||
xts_mode = 0
|
||||
aes_region_lock = 0
|
||||
no_segment = 1
|
||||
boot2_enable = 0
|
||||
boot2_rollback = 0
|
||||
cpu_master_id = 0
|
||||
notload_in_bootrom = 0
|
||||
crc_ignore = 0
|
||||
hash_ignore = 0
|
||||
power_on_mm = 1
|
||||
em_sel = 1
|
||||
cmds_en = 1
|
||||
#0:cmds bypass wrap commands to macro, original mode;
|
||||
#1:cmds handle wrap commands, original mode;
|
||||
#2:cmds bypass wrap commands to macro, cmds force wrap16*4 splitted into two wrap8*4;
|
||||
#3:cmds handle wrap commands, cmds force wrap16*4 splitted into two wrap8*4
|
||||
cmds_wrap_mode = 2
|
||||
#0:SF_CTRL_WRAP_LEN_8, 1:SF_CTRL_WRAP_LEN_16, 2:SF_CTRL_WRAP_LEN_32,
|
||||
#3:SF_CTRL_WRAP_LEN_64, 9: SF_CTRL_WRAP_LEN_4096
|
||||
cmds_wrap_len = 2
|
||||
icache_invalid = 1
|
||||
dcache_invalid = 1
|
||||
fpga_halt_release = 0
|
||||
|
||||
########################image cfg####################################
|
||||
#flash controller offset
|
||||
group_image_offset = 0x2000
|
||||
aes_region_len = 0
|
||||
|
||||
#total image len or segment count
|
||||
img_len_cnt = 0x100
|
||||
#img hash
|
||||
hash_0 = 0xdeadbeef
|
||||
hash_1 = 0
|
||||
hash_2 = 0
|
||||
hash_3 = 0
|
||||
hash_4 = 0
|
||||
hash_5 = 0
|
||||
hash_6 = 0
|
||||
hash_7 = 0
|
||||
|
||||
########################CPU M0 cfg###################################
|
||||
m0_config_enable = 1
|
||||
m0_halt_cpu = 0
|
||||
m0_cache_enable = 0
|
||||
m0_cache_wa = 0
|
||||
m0_cache_wb = 0
|
||||
m0_cache_wt = 0
|
||||
m0_cache_way_dis = 0
|
||||
m0_reserved = 0
|
||||
|
||||
#img RAM address or flash offset
|
||||
m0_image_address_offset = 0x0
|
||||
m0_boot_entry = 0xA0000000
|
||||
m0_msp_val = 0
|
||||
|
||||
boot2_pt_table_0 = 0
|
||||
boot2_pt_table_1 = 0
|
||||
|
||||
flashCfgTableAddr = 0
|
||||
flashCfgTableLen = 0
|
||||
|
||||
########################patch on read################################
|
||||
patch_read_addr0 = 0
|
||||
patch_read_value0 = 0
|
||||
patch_read_addr1 = 0
|
||||
patch_read_value1 = 0
|
||||
patch_read_addr2 = 0
|
||||
patch_read_value2 = 0
|
||||
|
||||
########################patch on jump################################
|
||||
patch_jump_addr0 = 0
|
||||
patch_jump_value0 = 0
|
||||
patch_jump_addr1 = 0
|
||||
patch_jump_value1 = 0
|
||||
patch_jump_addr2 = 0
|
||||
patch_jump_value2 = 0
|
||||
|
||||
reserved = 0
|
||||
|
||||
crc32 = 0xdeadbeef
|
||||
BIN
chips/bl616/efuse_bootheader/flash_para.bin
Normal file
BIN
chips/bl616/efuse_bootheader/flash_para.bin
Normal file
Binary file not shown.
BIN
chips/bl616/img_create/whole_flash_data.bin
Normal file
BIN
chips/bl616/img_create/whole_flash_data.bin
Normal file
Binary file not shown.
BIN
chips/bl616/img_create/whole_img.pack
Normal file
BIN
chips/bl616/img_create/whole_img.pack
Normal file
Binary file not shown.
BIN
chips/bl702/eflash_loader/eflash_loader.elf
Normal file
BIN
chips/bl702/eflash_loader/eflash_loader.elf
Normal file
Binary file not shown.
14715
chips/bl702/eflash_loader/eflash_loader.map
Normal file
14715
chips/bl702/eflash_loader/eflash_loader.map
Normal file
File diff suppressed because it is too large
Load Diff
BIN
chips/bl702/eflash_loader/eflash_loader_32m.bin
Normal file
BIN
chips/bl702/eflash_loader/eflash_loader_32m.bin
Normal file
Binary file not shown.
67
chips/bl702/eflash_loader/eflash_loader_cfg.conf
Normal file
67
chips/bl702/eflash_loader/eflash_loader_cfg.conf
Normal file
|
|
@ -0,0 +1,67 @@
|
|||
[LOAD_CFG]
|
||||
#jlink or uart
|
||||
interface = uart
|
||||
device = COM1
|
||||
speed_uart_boot = 500000
|
||||
speed_uart_load = 500000
|
||||
#cklink usb vid|pid
|
||||
cklink_vidpid = 42bf|b210
|
||||
cklink_type = CKLink_Lite_Vendor-rog
|
||||
#eg: rv_dbg_plus, ft2232hl, ft2232d
|
||||
openocd_config = rv_dbg_plus
|
||||
auto_burn = false
|
||||
speed_jlink = 2000
|
||||
#0:without load, 1:eflash_loader load
|
||||
load_function = 1
|
||||
do_reset = true
|
||||
#reset retry+hold time
|
||||
reset_hold_time = 50
|
||||
shake_hand_delay = 100
|
||||
reset_revert = false
|
||||
cutoff_time = 50
|
||||
shake_hand_retry = 3
|
||||
flash_burn_retry = 1
|
||||
checksum_err_retry = 3
|
||||
#1: 32M, 2: RC32M
|
||||
#xtal_type = 2
|
||||
erase_time_out = 15000
|
||||
#chiptype=702
|
||||
eflash_loader_file=chips/bl702/eflash_loader/eflash_loader_32m.bin
|
||||
check_mac = true
|
||||
#0:no erase,1:programmed section erase,2:chip erase
|
||||
erase = 1
|
||||
# switch eflash_loader command log save
|
||||
local_log = false
|
||||
#0:verify by calculating SHA256(xip), >0:read back verify and verify by calculating SHA256(sbus)
|
||||
verify = 0
|
||||
tx_size = 2056
|
||||
cpu_reset_after_load = false
|
||||
#skip mode set first para is skip addr, second para is skip len
|
||||
skip_mode = 0x0, 0x0
|
||||
boot2_isp_mode = 0
|
||||
isp_mode_speed = 2000000
|
||||
isp_shakehand_timeout = 0
|
||||
|
||||
[FLASH_CFG]
|
||||
flash_id = c84015
|
||||
#flash clock 0:72M, 1:36M, 2:24M, 3:18M
|
||||
flash_clock_cfg = 2
|
||||
#0:NIO, 1:DO, 2:QO, 3:DIO, 4:QIO
|
||||
flash_io_mode = 1
|
||||
#flash_pin value:
|
||||
#bit 2-3 = flash_cfg: 0: external gpio 23-28, 1: internal 512K, 2: internal 1M, 3: external gpio 17-22
|
||||
#bit 0-1 = swap_cfg: 0: do not swap, 1: swap cs&io2, 2: swap io0&io3, 3: swap cs&io2 io0&io3 both
|
||||
flash_pin = ""
|
||||
#empty for auto, otherwise specified para file path: eg: chips/bl702/efuse_bootheader/flash_para.bin
|
||||
flash_para = chips/bl702/efuse_bootheader/flash_para.bin
|
||||
decompress_write = false
|
||||
file = chips/bl702/img_create/bootinfo_boot2.bin chips/bl702/img_create/img_boot2.bin chips/bl702/partition/partition.bin chips/bl702/partition/partition.bin
|
||||
address = 00000000 00002000 e000 f000
|
||||
|
||||
[EFUSE_CFG]
|
||||
burn_en = true
|
||||
factory_mode = false
|
||||
security_write = false
|
||||
security_save = true
|
||||
file = ../../../Tools/img_tools/efuse_bootheader/efusedata.bin
|
||||
maskfile = ../../../Tools/img_tools/efuse_bootheader/efusedata_mask.bin
|
||||
196
chips/bl702/efuse_bootheader/efuse_bootheader_cfg.conf
Normal file
196
chips/bl702/efuse_bootheader/efuse_bootheader_cfg.conf
Normal file
|
|
@ -0,0 +1,196 @@
|
|||
[EFUSE_CFG]
|
||||
########################################################################
|
||||
#2bits
|
||||
ef_sf_aes_mode = 0
|
||||
#2bits
|
||||
ef_sboot_sign_mode = 0
|
||||
#2bits
|
||||
ef_sboot_en = 0
|
||||
#2bits
|
||||
ef_dbg_jtag_dis = 0
|
||||
#4bits
|
||||
ef_dbg_mode = 0
|
||||
#32bits
|
||||
ef_dbg_pwd_low = 0
|
||||
#32bits
|
||||
ef_dbg_pwd_high = 0
|
||||
###################################################################
|
||||
ef_key_slot_2_w0 = 0
|
||||
ef_key_slot_2_w1 = 0
|
||||
ef_key_slot_2_w2 = 0
|
||||
ef_key_slot_2_w3 = 0
|
||||
ef_key_slot_3_w0 = 0
|
||||
ef_key_slot_3_w1 = 0
|
||||
ef_key_slot_3_w2 = 0
|
||||
ef_key_slot_3_w3 = 0
|
||||
ef_key_slot_4_w0 = 0
|
||||
ef_key_slot_4_w1 = 0
|
||||
ef_key_slot_4_w2 = 0
|
||||
ef_key_slot_4_w3 = 0
|
||||
|
||||
wr_lock_key_slot_4_l = 0
|
||||
wr_lock_dbg_pwd = 0
|
||||
wr_lock_key_slot_2 = 0
|
||||
wr_lock_key_slot_3 = 0
|
||||
wr_lock_key_slot_4_h = 0
|
||||
rd_lock_dbg_pwd = 0
|
||||
rd_lock_key_slot_2 = 0
|
||||
rd_lock_key_slot_3 = 0
|
||||
rd_lock_key_slot_4 = 0
|
||||
|
||||
[BOOTHEADER_CFG]
|
||||
magic_code = 0x504e4642
|
||||
revision = 0x01
|
||||
#########################flash cfg#############################
|
||||
flashcfg_magic_code = 0x47464346
|
||||
#flashcfg_magic_code=0
|
||||
io_mode = 0x10
|
||||
cont_read_support = 0
|
||||
sfctrl_clk_delay = 0
|
||||
sfctrl_clk_invert = 0x03
|
||||
|
||||
reset_en_cmd = 0x66
|
||||
reset_cmd = 0x99
|
||||
exit_contread_cmd = 0xff
|
||||
exit_contread_cmd_size = 3
|
||||
|
||||
jedecid_cmd = 0x9f
|
||||
jedecid_cmd_dmy_clk = 0
|
||||
qpi_jedecid_cmd = 0x9f
|
||||
qpi_jedecid_dmy_clk = 0
|
||||
|
||||
sector_size = 4
|
||||
mfg_id = 0xff
|
||||
page_size = 256
|
||||
|
||||
chip_erase_cmd = 0xc7
|
||||
sector_erase_cmd = 0x20
|
||||
blk32k_erase_cmd = 0x52
|
||||
blk64k_erase_cmd = 0xd8
|
||||
|
||||
write_enable_cmd = 0x06
|
||||
page_prog_cmd = 0x02
|
||||
qpage_prog_cmd = 0x32
|
||||
qual_page_prog_addr_mode = 0
|
||||
|
||||
fast_read_cmd = 0x0b
|
||||
fast_read_dmy_clk = 1
|
||||
qpi_fast_read_cmd = 0x0b
|
||||
qpi_fast_read_dmy_clk = 1
|
||||
|
||||
fast_read_do_cmd = 0x3b
|
||||
fast_read_do_dmy_clk = 1
|
||||
fast_read_dio_cmd = 0xbb
|
||||
fast_read_dio_dmy_clk = 0
|
||||
|
||||
fast_read_qo_cmd = 0x6b
|
||||
fast_read_qo_dmy_clk = 1
|
||||
fast_read_qio_cmd = 0xeb
|
||||
fast_read_qio_dmy_clk = 2
|
||||
|
||||
qpi_fast_read_qio_cmd = 0xeb
|
||||
qpi_fast_read_qio_dmy_clk = 2
|
||||
qpi_page_prog_cmd = 0x02
|
||||
write_vreg_enable_cmd = 0x50
|
||||
|
||||
wel_reg_index = 0
|
||||
qe_reg_index = 1
|
||||
busy_reg_index = 0
|
||||
wel_bit_pos = 1
|
||||
|
||||
qe_bit_pos = 1
|
||||
busy_bit_pos = 0
|
||||
wel_reg_write_len = 2
|
||||
wel_reg_read_len = 1
|
||||
|
||||
qe_reg_write_len = 2
|
||||
qe_reg_read_len = 1
|
||||
release_power_down = 0xab
|
||||
busy_reg_read_len = 1
|
||||
|
||||
reg_read_cmd0 = 0x05
|
||||
reg_read_cmd1 = 0x35
|
||||
|
||||
reg_write_cmd0 = 0x01
|
||||
reg_write_cmd1 = 0x01
|
||||
|
||||
enter_qpi_cmd = 0x38
|
||||
exit_qpi_cmd = 0xff
|
||||
cont_read_code = 0xa0
|
||||
cont_read_exit_code = 0xff
|
||||
|
||||
burst_wrap_cmd = 0x77
|
||||
burst_wrap_dmy_clk = 0x03
|
||||
burst_wrap_data_mode = 2
|
||||
burst_wrap_code = 0x40
|
||||
|
||||
de_burst_wrap_cmd = 0x77
|
||||
de_burst_wrap_cmd_dmy_clk = 0x03
|
||||
de_burst_wrap_code_mode = 2
|
||||
de_burst_wrap_code = 0xF0
|
||||
|
||||
sector_erase_time = 300
|
||||
blk32k_erase_time = 1200
|
||||
|
||||
blk64k_erase_time = 1200
|
||||
page_prog_time = 5
|
||||
|
||||
chip_erase_time = 200000
|
||||
power_down_delay = 20
|
||||
qe_data = 0
|
||||
|
||||
flashcfg_crc32 = 0
|
||||
|
||||
#########################clk cfg####################################
|
||||
clkcfg_magic_code = 0x47464350
|
||||
#clkcfg_magic_code=0
|
||||
|
||||
#0:Not use XTAL to set PLL, 1:XTAL is 32M, 2:XTAL is RC32M
|
||||
xtal_type = 1
|
||||
#0:RC32M, 1:XTAL, 2:PLL 57.6M, 3:PLL 96M, 4:PLL 144M
|
||||
pll_clk = 1
|
||||
hclk_div = 0
|
||||
bclk_div = 0
|
||||
#0:144M, 1:XCLK(RC32M or XTAL), 2:57.6M, 3:72M, 4:BCLK, 5:96M
|
||||
flash_clk_type = 1
|
||||
flash_clk_div = 0
|
||||
clkcfg_crc32 = 0
|
||||
|
||||
########################boot cfg####################################
|
||||
#1:ECC
|
||||
sign = 0
|
||||
#1:AES128,2:AES256,3:AES192
|
||||
encrypt_type = 0
|
||||
key_sel = 1
|
||||
no_segment = 1
|
||||
cache_enable = 1
|
||||
notload_in_bootrom = 0
|
||||
aes_region_lock = 0
|
||||
cache_way_disable = 0x00
|
||||
crc_ignore = 1
|
||||
hash_ignore = 1
|
||||
boot2_enable=1
|
||||
boot2_rollback=0
|
||||
|
||||
########################image cfg####################################
|
||||
#total image len or segment count
|
||||
img_len = 0x100
|
||||
bootentry = 0
|
||||
#img RAM address or flash offset
|
||||
img_start = 0x2000
|
||||
|
||||
#img hash
|
||||
hash_0 = 0xdeadbeef
|
||||
hash_1 = 0
|
||||
hash_2 = 0
|
||||
hash_3 = 0
|
||||
hash_4 = 0
|
||||
hash_5 = 0
|
||||
hash_6 = 0
|
||||
hash_7 = 0
|
||||
|
||||
#address of partition tables for boot2 in bootrom
|
||||
boot2_pt_table_0=0x1000
|
||||
boot2_pt_table_1=0x2000
|
||||
|
||||
crc32 = 0xdeadbeef
|
||||
82
chips/bl702l/eflash_loader/eflash_loader_cfg.conf
Normal file
82
chips/bl702l/eflash_loader/eflash_loader_cfg.conf
Normal file
|
|
@ -0,0 +1,82 @@
|
|||
[LOAD_CFG]
|
||||
#jlink or uart
|
||||
interface = uart
|
||||
device = COM1
|
||||
speed_uart_boot = 500000
|
||||
speed_uart_load = 500000
|
||||
#cklink usb vid|pid
|
||||
cklink_vidpid = 42bf|b210
|
||||
cklink_type = CKLink_Lite_Vendor-rog
|
||||
#eg: rv_dbg_plus, ft2232hl, ft2232d
|
||||
openocd_config = rv_dbg_plus
|
||||
auto_burn = false
|
||||
speed_jlink = 2000
|
||||
#0:without load, 1:eflash_loader load, 2: bootrom load
|
||||
load_function = 2
|
||||
do_reset = true
|
||||
#reset retry+hold time
|
||||
reset_hold_time = 50
|
||||
shake_hand_delay = 100
|
||||
reset_revert = false
|
||||
cutoff_time = 50
|
||||
shake_hand_retry = 3
|
||||
flash_burn_retry = 1
|
||||
checksum_err_retry = 3
|
||||
#1: 32M, 2: RC32M
|
||||
#xtal_type = 2
|
||||
erase_time_out = 15000
|
||||
#chiptype=702l
|
||||
eflash_loader_file=chips/bl702l/eflash_loader/eflash_loader_32m.bin
|
||||
check_mac = true
|
||||
#0:no erase,1:programmed section erase,2:chip erase
|
||||
erase = 1
|
||||
# switch eflash_loader command log save
|
||||
local_log = false
|
||||
#0:verify by calculating SHA256(xip), >0:read back verify and verify by calculating SHA256(sbus)
|
||||
verify = 0
|
||||
tx_size = 2056
|
||||
cpu_reset_after_load = false
|
||||
#empty for auto, otherwise specified clock para file path: eg: chips/bl702l/efuse_bootheader/clock_para.bin
|
||||
clock_para = chips/bl702l/efuse_bootheader/clock_para.bin
|
||||
#skip mode set first para is skip addr, second para is skip len
|
||||
skip_mode = 0x0, 0x0
|
||||
boot2_isp_mode = 0
|
||||
isp_mode_speed = 2000000
|
||||
isp_shakehand_timeout = 0
|
||||
|
||||
[FLASH_CFG]
|
||||
flash_id = c84015
|
||||
#bit 7-4 flash_clock_type: 0:XCLK(RC32M or XTAL), 1:64M, 2:BCLK, 3:42.67M
|
||||
#bit 3-0 flash_clock_div
|
||||
flash_clock_cfg = 0
|
||||
#0:0.5T delay, 1:1T delay, 2:1.5T delay
|
||||
flash_clock_delay = 1
|
||||
#0:NIO, 1:DO, 2:QO, 3:DIO, 4:QIO
|
||||
flash_io_mode = 1
|
||||
#flash_pin value:
|
||||
#bit 7 flash pin set from efuse flash cfg
|
||||
#bit 6-0 flash pin cfg:
|
||||
#0x0: sf2 external flash use GPIO23-28
|
||||
#0x1: sf1 embedded flash no swap
|
||||
#0x2: sf1 embedded flash swap io2 with cs
|
||||
#0x3: sf1 embedded flash swap io3 with io0
|
||||
#0x4: sf1 embedded flash swap io3 with io0 and io2 with cs
|
||||
#0x5: sf1 embedded flash interface reverse and no swap
|
||||
#0x6: sf1 embedded flash interface reverse and swap io2 with cs
|
||||
#0x7: sf1 embedded flash interface reverse and swap io3 with io0
|
||||
#0x8: sf1 embedded flash interface reverse and swap io3 with io0 and io2 with cs
|
||||
#0x80:flash pin set from efuse flash cfg
|
||||
flash_pin = 0x80
|
||||
#empty for auto, otherwise specified para file path: eg: chips/bl702l/efuse_bootheader/flash_para.bin
|
||||
flash_para = chips/bl702l/efuse_bootheader/flash_para.bin
|
||||
decompress_write = true
|
||||
file = chips/bl702l/img_create/bootinfo_boot2.bin chips/bl702l/img_create/img_boot2.bin chips/bl702l/partition/partition.bin chips/bl702l/partition/partition.bin
|
||||
address = 00000000 00002000 e000 f000
|
||||
|
||||
[EFUSE_CFG]
|
||||
burn_en = true
|
||||
factory_mode = false
|
||||
security_write = false
|
||||
security_save = true
|
||||
file = ../../../Tools/img_tools/efuse_bootheader/efusedata.bin
|
||||
maskfile = ../../../Tools/img_tools/efuse_bootheader/efusedata_mask.bin
|
||||
218
chips/bl702l/efuse_bootheader/efuse_bootheader_cfg.conf
Normal file
218
chips/bl702l/efuse_bootheader/efuse_bootheader_cfg.conf
Normal file
|
|
@ -0,0 +1,218 @@
|
|||
[EFUSE_CFG]
|
||||
########################################################################
|
||||
#2bits
|
||||
ef_sf_aes_mode = 0
|
||||
#2bits
|
||||
ef_sboot_sign_mode = 0
|
||||
#2bits
|
||||
ef_sboot_en = 0
|
||||
#2bits
|
||||
ef_dbg_jtag_dis = 0
|
||||
#4bits
|
||||
ef_dbg_mode = 0
|
||||
#32bits
|
||||
ef_dbg_pwd_low = 0
|
||||
#32bits
|
||||
ef_dbg_pwd_high = 0
|
||||
###################################################################
|
||||
ef_key_slot_2_w0 = 0
|
||||
ef_key_slot_2_w1 = 0
|
||||
ef_key_slot_2_w2 = 0
|
||||
ef_key_slot_2_w3 = 0
|
||||
ef_key_slot_3_w0 = 0
|
||||
ef_key_slot_3_w1 = 0
|
||||
ef_key_slot_3_w2 = 0
|
||||
ef_key_slot_3_w3 = 0
|
||||
ef_key_slot_4_w0 = 0
|
||||
ef_key_slot_4_w1 = 0
|
||||
ef_key_slot_4_w2 = 0
|
||||
ef_key_slot_4_w3 = 0
|
||||
|
||||
wr_lock_key_slot_4_l = 0
|
||||
wr_lock_dbg_pwd = 0
|
||||
wr_lock_key_slot_2 = 0
|
||||
wr_lock_key_slot_3 = 0
|
||||
wr_lock_key_slot_4_h = 0
|
||||
rd_lock_dbg_pwd = 0
|
||||
rd_lock_key_slot_2 = 0
|
||||
rd_lock_key_slot_3 = 0
|
||||
rd_lock_key_slot_4 = 0
|
||||
|
||||
[BOOTHEADER_CFG]
|
||||
magic_code = 0x504e4642
|
||||
revision = 0x01
|
||||
#########################flash cfg#############################
|
||||
flashcfg_magic_code = 0x47464346
|
||||
#flashcfg_magic_code=0
|
||||
io_mode = 0x10
|
||||
cont_read_support = 0
|
||||
sfctrl_clk_delay = 1
|
||||
sfctrl_clk_invert = 0x01
|
||||
|
||||
reset_en_cmd = 0x66
|
||||
reset_cmd = 0x99
|
||||
exit_contread_cmd = 0xff
|
||||
exit_contread_cmd_size = 3
|
||||
|
||||
jedecid_cmd = 0x9f
|
||||
jedecid_cmd_dmy_clk = 0
|
||||
qpi_jedecid_cmd = 0x9f
|
||||
qpi_jedecid_dmy_clk = 0
|
||||
|
||||
sector_size = 4
|
||||
mfg_id = 0xff
|
||||
page_size = 256
|
||||
|
||||
chip_erase_cmd = 0xc7
|
||||
sector_erase_cmd = 0x20
|
||||
blk32k_erase_cmd = 0x52
|
||||
blk64k_erase_cmd = 0xd8
|
||||
|
||||
write_enable_cmd = 0x06
|
||||
page_prog_cmd = 0x02
|
||||
qpage_prog_cmd = 0x32
|
||||
qual_page_prog_addr_mode = 0
|
||||
|
||||
fast_read_cmd = 0x0b
|
||||
fast_read_dmy_clk = 1
|
||||
qpi_fast_read_cmd = 0x0b
|
||||
qpi_fast_read_dmy_clk = 1
|
||||
|
||||
fast_read_do_cmd = 0x3b
|
||||
fast_read_do_dmy_clk = 1
|
||||
fast_read_dio_cmd = 0xbb
|
||||
fast_read_dio_dmy_clk = 0
|
||||
|
||||
fast_read_qo_cmd = 0x6b
|
||||
fast_read_qo_dmy_clk = 1
|
||||
fast_read_qio_cmd = 0xeb
|
||||
fast_read_qio_dmy_clk = 2
|
||||
|
||||
qpi_fast_read_qio_cmd = 0xeb
|
||||
qpi_fast_read_qio_dmy_clk = 2
|
||||
qpi_page_prog_cmd = 0x02
|
||||
write_vreg_enable_cmd = 0x50
|
||||
|
||||
wel_reg_index = 0
|
||||
qe_reg_index = 1
|
||||
busy_reg_index = 0
|
||||
wel_bit_pos = 1
|
||||
|
||||
qe_bit_pos = 1
|
||||
busy_bit_pos = 0
|
||||
wel_reg_write_len = 2
|
||||
wel_reg_read_len = 1
|
||||
|
||||
qe_reg_write_len = 2
|
||||
qe_reg_read_len = 1
|
||||
release_power_down = 0xab
|
||||
busy_reg_read_len = 1
|
||||
|
||||
reg_read_cmd0 = 0x05
|
||||
reg_read_cmd1 = 0x35
|
||||
|
||||
reg_write_cmd0 = 0x01
|
||||
reg_write_cmd1 = 0x01
|
||||
|
||||
enter_qpi_cmd = 0x38
|
||||
exit_qpi_cmd = 0xff
|
||||
cont_read_code = 0xa0
|
||||
cont_read_exit_code = 0xff
|
||||
|
||||
burst_wrap_cmd = 0x77
|
||||
burst_wrap_dmy_clk = 0x03
|
||||
burst_wrap_data_mode = 2
|
||||
burst_wrap_code = 0x40
|
||||
|
||||
de_burst_wrap_cmd = 0x77
|
||||
de_burst_wrap_cmd_dmy_clk = 0x03
|
||||
de_burst_wrap_code_mode = 2
|
||||
de_burst_wrap_code = 0xF0
|
||||
|
||||
sector_erase_time = 300
|
||||
blk32k_erase_time = 1200
|
||||
|
||||
blk64k_erase_time = 1200
|
||||
page_prog_time = 5
|
||||
|
||||
chip_erase_time = 33000
|
||||
power_down_delay = 20
|
||||
qe_data = 0
|
||||
|
||||
flashcfg_crc32 = 0
|
||||
|
||||
#########################clk cfg####################################
|
||||
clkcfg_magic_code = 0x47464350
|
||||
#clkcfg_magic_code=0
|
||||
|
||||
#0:Not use XTAL to set PLL, 1:XTAL is 32M, 2:XTAL is RC32M
|
||||
xtal_type = 1
|
||||
#0:RC32M, 1:XTAL, 2:DLL 26.6M, 3:DLL 42.67M, 4:DLL 64M, 5:DLL 128M
|
||||
pll_clk = 5
|
||||
hclk_div = 0
|
||||
bclk_div = 1
|
||||
#0:XCLK(RC32M or XTAL), 1:64M, 2:BCLK, 3:42.67M
|
||||
flash_clk_type = 0
|
||||
flash_clk_div = 0
|
||||
clkcfg_crc32 = 0
|
||||
|
||||
########################boot cfg####################################
|
||||
#1:ECC
|
||||
sign = 0
|
||||
#1:AES128,2:AES256,3:AES192
|
||||
encrypt_type = 0
|
||||
key_sel = 1
|
||||
no_segment = 1
|
||||
cache_enable = 1
|
||||
notload_in_bootrom = 0
|
||||
aes_region_lock = 0
|
||||
cache_way_disable = 0x00
|
||||
crc_ignore = 1
|
||||
hash_ignore = 1
|
||||
boot2_enable=1
|
||||
boot2_rollback=0
|
||||
|
||||
########################image cfg####################################
|
||||
#total image len or segment count
|
||||
img_len = 0x100
|
||||
bootentry = 0
|
||||
#img RAM address or flash offset
|
||||
img_start = 0x2000
|
||||
|
||||
#img hash
|
||||
hash_0 = 0xdeadbeef
|
||||
hash_1 = 0
|
||||
hash_2 = 0
|
||||
hash_3 = 0
|
||||
hash_4 = 0
|
||||
hash_5 = 0
|
||||
hash_6 = 0
|
||||
hash_7 = 0
|
||||
|
||||
#address of partition tables for boot2 in bootrom
|
||||
boot2_pt_table_0=0x1000
|
||||
boot2_pt_table_1=0x2000
|
||||
|
||||
flashCfgTableAddr = 0
|
||||
flashCfgTableLen = 0
|
||||
|
||||
########################patch on read################################
|
||||
patch_read_addr0 = 0
|
||||
patch_read_value0 = 0
|
||||
patch_read_addr1 = 0
|
||||
patch_read_value1 = 0
|
||||
patch_read_addr2 = 0
|
||||
patch_read_value2 = 0
|
||||
|
||||
########################patch on jump################################
|
||||
patch_jump_addr0 = 0
|
||||
patch_jump_value0 = 0
|
||||
patch_jump_addr1 = 0
|
||||
patch_jump_value1 = 0
|
||||
patch_jump_addr2 = 0
|
||||
patch_jump_value2 = 0
|
||||
|
||||
reserved1 = 0
|
||||
reserved2 = 0
|
||||
|
||||
crc32 = 0xdeadbeef
|
||||
69
chips/bl808/eflash_loader/eflash_loader_cfg.conf
Normal file
69
chips/bl808/eflash_loader/eflash_loader_cfg.conf
Normal file
|
|
@ -0,0 +1,69 @@
|
|||
[LOAD_CFG]
|
||||
#jlink or uart
|
||||
interface = uart
|
||||
device = COM1
|
||||
speed_uart_boot = 500000
|
||||
speed_uart_load = 2000000
|
||||
#cklink usb vid|pid
|
||||
cklink_vidpid = 42bf|b210
|
||||
cklink_type = CKLink_Lite_Vendor-rog
|
||||
#eg: rv_dbg_plus, ft2232hl, ft2232d
|
||||
openocd_config = rv_dbg_plus
|
||||
auto_burn = false
|
||||
speed_jlink = 1000
|
||||
#0:without load, 1:eflash_loader load, 2: bootrom load
|
||||
load_function = 2
|
||||
do_reset = true
|
||||
#reset retry+hold time
|
||||
reset_hold_time = 50
|
||||
shake_hand_delay = 100
|
||||
reset_revert = false
|
||||
cutoff_time = 50
|
||||
shake_hand_retry = 3
|
||||
flash_burn_retry = 1
|
||||
checksum_err_retry = 3
|
||||
erase_time_out = 100000
|
||||
#chiptype=bl808
|
||||
check_mac = true
|
||||
#0:no erase,1:programmed section erase,2:chip erase
|
||||
erase = 1
|
||||
# switch eflash_loader command log save
|
||||
local_log = false
|
||||
#0:verify by calculating SHA256(xip), >0:read back verify and verify by calculating SHA256(sbus)
|
||||
verify = 0
|
||||
tx_size = 4104
|
||||
cpu_reset_after_load = false
|
||||
#empty for auto, otherwise specified clock para file path: eg: chips/bl808/efuse_bootheader/clock_para.bin
|
||||
clock_para = chips/bl808/efuse_bootheader/clock_para.bin
|
||||
#skip mode set first para is skip addr, second para is skip len
|
||||
skip_mode = 0x0, 0x0
|
||||
boot2_isp_mode = 0
|
||||
isp_mode_speed = 2000000
|
||||
isp_shakehand_timeout = 0
|
||||
|
||||
[FLASH_CFG]
|
||||
flash_id = ef4016
|
||||
#bit 7-4 flash_clock_type: 0:120M wifipll, 1:xtal, 2:128M cpupll, 3:80M wifipll, 4:bclk, 5:96M wifipll
|
||||
#bit 3-0 flash_clock_div
|
||||
flash_clock_cfg = 0x41
|
||||
#0:0.5T delay, 1:1T delay, 2:1.5T delay, 3:2T delay
|
||||
flash_clock_delay = 0
|
||||
#0:NIO, 1:DO, 2:QO, 3:DIO, 4:QIO
|
||||
flash_io_mode = 1
|
||||
#flash_pin value:
|
||||
#bit 7 flash pin autoscan
|
||||
#bit 6-0 flash pin cfg: 0: internal swap io0 with io3, 2: internal no swap io0 with io3, 4: external gpi34-39,
|
||||
flash_pin = 0x80
|
||||
#empty for auto, otherwise specified flash para file path: eg: chips/bl808/efuse_bootheader/flash_para.bin
|
||||
flash_para = chips/bl808/efuse_bootheader/flash_para.bin
|
||||
decompress_write = false
|
||||
file = chips/bl808/img_create2/whole_img.bin
|
||||
address = 00000000
|
||||
|
||||
[EFUSE_CFG]
|
||||
burn_en = true
|
||||
factory_mode = false
|
||||
security_write = false
|
||||
security_save = true
|
||||
file = ../../../Tools/img_tools/efuse_bootheader/efusedata.bin
|
||||
maskfile = ../../../Tools/img_tools/efuse_bootheader/efusedata_mask.bin
|
||||
520
chips/bl808/efuse_bootheader/efuse_bootheader_cfg.conf
Normal file
520
chips/bl808/efuse_bootheader/efuse_bootheader_cfg.conf
Normal file
|
|
@ -0,0 +1,520 @@
|
|||
[EFUSE_CFG]
|
||||
########################################################################
|
||||
ef_sf_aes_mode=0
|
||||
ef_no_xtal=0
|
||||
ef_force_no_trim=0
|
||||
ef_sf_key_re_sel=0
|
||||
ef_dbg_jtag_0_dis=0
|
||||
###################################################################
|
||||
ef_dbg_pwd_low=0
|
||||
ef_dbg_pwd_high=0
|
||||
ef_dbg_pwd2_low=0
|
||||
ef_dbg_pwd2_high=0
|
||||
ef_wifi_mac_low=0
|
||||
ef_wifi_mac_high=0
|
||||
ef_key_slot_0_w0=0
|
||||
ef_key_slot_0_w1=0
|
||||
ef_key_slot_0_w2=0
|
||||
ef_key_slot_0_w3=0
|
||||
ef_key_slot_1_w0=0
|
||||
ef_key_slot_1_w1=0
|
||||
ef_key_slot_1_w2=0
|
||||
ef_key_slot_1_w3=0
|
||||
ef_key_slot_2_w0=0
|
||||
ef_key_slot_2_w1=0
|
||||
ef_key_slot_2_w2=0
|
||||
ef_key_slot_2_w3=0
|
||||
ef_key_slot_3_w0=0
|
||||
ef_key_slot_3_w1=0
|
||||
ef_key_slot_3_w2=0
|
||||
ef_key_slot_3_w3=0
|
||||
##########################################
|
||||
ef_sw_usage_0=0
|
||||
ef_sw_usage_1=0
|
||||
ef_sw_usage_2=0
|
||||
ef_sw_usage_3=0
|
||||
ef_key_slot_11_w0=0
|
||||
ef_key_slot_11_w1=0
|
||||
ef_key_slot_11_w2=0
|
||||
ef_key_slot_11_w3=0
|
||||
###################################################################
|
||||
ef_sec_lifecycle=0
|
||||
wr_lock_rsvd_0=0
|
||||
wr_lock_boot_mode=0
|
||||
wr_lock_dbg_pwd=0
|
||||
wr_lock_wifi_mac=0
|
||||
wr_lock_key_slot_0=0
|
||||
wr_lock_key_slot_1=0
|
||||
wr_lock_key_slot_2=0
|
||||
wr_lock_key_slot_3=0
|
||||
wr_lock_sw_usage_0=0
|
||||
wr_lock_sw_usage_1=0
|
||||
wr_lock_sw_usage_2=0
|
||||
wr_lock_sw_usage_3=0
|
||||
wr_lock_key_slot_11=0
|
||||
rd_lock_dbg_pwd=0
|
||||
rd_lock_key_slot_0=0
|
||||
rd_lock_key_slot_1=0
|
||||
rd_lock_key_slot_2=0
|
||||
rd_lock_key_slot_3=0
|
||||
rd_lock_key_slot_11=0
|
||||
########################################################################
|
||||
ef_key_slot_4_w0=0
|
||||
ef_key_slot_4_w1=0
|
||||
ef_key_slot_4_w2=0
|
||||
ef_key_slot_4_w3=0
|
||||
ef_key_slot_5_w0=0
|
||||
ef_key_slot_5_w1=0
|
||||
ef_key_slot_5_w2=0
|
||||
ef_key_slot_5_w3=0
|
||||
ef_key_slot_6_w0=0
|
||||
ef_key_slot_6_w1=0
|
||||
ef_key_slot_6_w2=0
|
||||
ef_key_slot_6_w3=0
|
||||
ef_key_slot_7_w0=0
|
||||
ef_key_slot_7_w1=0
|
||||
ef_key_slot_7_w2=0
|
||||
ef_key_slot_7_w3=0
|
||||
ef_key_slot_8_w0=0
|
||||
ef_key_slot_8_w1=0
|
||||
ef_key_slot_8_w2=0
|
||||
ef_key_slot_8_w3=0
|
||||
ef_key_slot_9_w0=0
|
||||
ef_key_slot_9_w1=0
|
||||
ef_key_slot_9_w2=0
|
||||
ef_key_slot_9_w3=0
|
||||
ef_key_slot_10_w0=0
|
||||
ef_key_slot_10_w1=0
|
||||
ef_key_slot_10_w2=0
|
||||
ef_key_slot_10_w3=0
|
||||
ef_dat_1_rsvd_0=0
|
||||
ef_dat_1_rsvd_1=0
|
||||
ef_dat_1_rsvd_2=0
|
||||
########################################################################
|
||||
wr_lock_rsvd_1=0
|
||||
wr_lock_key_slot_4=0
|
||||
wr_lock_key_slot_5=0
|
||||
wr_lock_key_slot_6=0
|
||||
wr_lock_key_slot_7=0
|
||||
wr_lock_key_slot_8=0
|
||||
wr_lock_key_slot_9=0
|
||||
wr_lock_key_slot_10=0
|
||||
wr_lock_dat_1_rsvd_0=0
|
||||
wr_lock_dat_1_rsvd_1=0
|
||||
wr_lock_dat_1_rsvd_2=0
|
||||
rd_lock_key_slot_4=0
|
||||
rd_lock_key_slot_5=0
|
||||
rd_lock_key_slot_6=0
|
||||
rd_lock_key_slot_7=0
|
||||
rd_lock_key_slot_8=0
|
||||
rd_lock_key_slot_9=0
|
||||
rd_lock_key_slot_10=0
|
||||
|
||||
[BOOTHEADER_GROUP0_CFG]
|
||||
magic_code=0x504e4642
|
||||
revision=0x01
|
||||
#########################flash cfg#############################
|
||||
flashcfg_magic_code=0x47464346
|
||||
#flashcfg_magic_code=0
|
||||
io_mode=0x10
|
||||
#0.5T sfctrl_clk_delay=0 sfctrl_clk_invert=3
|
||||
#1 T sfctrl_clk_delay=1 sfctrl_clk_invert=1
|
||||
#1.5T sfctrl_clk_delay=1 sfctrl_clk_invert=3
|
||||
cont_read_support=0
|
||||
sfctrl_clk_delay=1
|
||||
sfctrl_clk_invert=0x01
|
||||
|
||||
reset_en_cmd=0x66
|
||||
reset_cmd=0x99
|
||||
exit_contread_cmd=0xff
|
||||
exit_contread_cmd_size=0x3
|
||||
|
||||
jedecid_cmd=0x9f
|
||||
jedecid_cmd_dmy_clk=0
|
||||
enter_32bits_addr_cmd=0xb7
|
||||
exit_32bits_addr_clk=0xe9
|
||||
|
||||
sector_size=4
|
||||
mfg_id=0xff
|
||||
page_size=256
|
||||
|
||||
chip_erase_cmd=0xc7
|
||||
sector_erase_cmd=0x20
|
||||
blk32k_erase_cmd=0x52
|
||||
blk64k_erase_cmd=0xd8
|
||||
|
||||
write_enable_cmd=0x06
|
||||
page_prog_cmd=0x02
|
||||
qpage_prog_cmd=0x32
|
||||
qual_page_prog_addr_mode=0
|
||||
|
||||
fast_read_cmd=0x0b
|
||||
fast_read_dmy_clk=1
|
||||
qpi_fast_read_cmd=0x0b
|
||||
qpi_fast_read_dmy_clk=1
|
||||
|
||||
fast_read_do_cmd=0x3b
|
||||
fast_read_do_dmy_clk=1
|
||||
fast_read_dio_cmd=0xbb
|
||||
fast_read_dio_dmy_clk=0
|
||||
|
||||
fast_read_qo_cmd=0x6b
|
||||
fast_read_qo_dmy_clk=1
|
||||
fast_read_qio_cmd=0xeb
|
||||
fast_read_qio_dmy_clk=2
|
||||
|
||||
qpi_fast_read_qio_cmd=0xeb
|
||||
qpi_fast_read_qio_dmy_clk=2
|
||||
qpi_page_prog_cmd=0x02
|
||||
write_vreg_enable_cmd=0x50
|
||||
|
||||
wel_reg_index=0
|
||||
qe_reg_index=1
|
||||
busy_reg_index=0
|
||||
wel_bit_pos=1
|
||||
|
||||
qe_bit_pos=1
|
||||
busy_bit_pos=0
|
||||
wel_reg_write_len=2
|
||||
wel_reg_read_len=1
|
||||
|
||||
qe_reg_write_len=2
|
||||
qe_reg_read_len=1
|
||||
release_power_down = 0xab
|
||||
busy_reg_read_len=1
|
||||
|
||||
reg_read_cmd0=0x05
|
||||
reg_read_cmd1=0x35
|
||||
|
||||
reg_write_cmd0=0x01
|
||||
reg_write_cmd1=0x01
|
||||
|
||||
enter_qpi_cmd=0x38
|
||||
exit_qpi_cmd=0xff
|
||||
cont_read_code=0x20
|
||||
cont_read_exit_code=0xf0
|
||||
|
||||
burst_wrap_cmd=0x77
|
||||
burst_wrap_dmy_clk=0x03
|
||||
burst_wrap_data_mode=2
|
||||
burst_wrap_code=0x40
|
||||
|
||||
de_burst_wrap_cmd=0x77
|
||||
de_burst_wrap_cmd_dmy_clk=0x03
|
||||
de_burst_wrap_code_mode=2
|
||||
de_burst_wrap_code=0xf0
|
||||
|
||||
sector_erase_time=300
|
||||
blk32k_erase_time=1200
|
||||
|
||||
blk64k_erase_time=1200
|
||||
|
||||
page_prog_time=50
|
||||
|
||||
chip_erase_time=200000
|
||||
power_down_delay = 20
|
||||
qe_data = 0
|
||||
|
||||
flashcfg_crc32=0
|
||||
|
||||
#########################clk cfg#####################################
|
||||
clkcfg_magic_code=0x47464350
|
||||
#clkcfg_magic_code=0
|
||||
|
||||
#0:None,1:24M,2:32M,3:38.4M,4:40M,5:26M,6:RC32M
|
||||
xtal_type=4
|
||||
#0:RC32M,1:Xtal,2:cpupll 400M,3:wifipll 192M,4:wifipll 320M
|
||||
mcu_clk=4
|
||||
mcu_clk_div=0
|
||||
mcu_bclk_div=0
|
||||
mcu_pbclk_div=3
|
||||
|
||||
lp_div=1
|
||||
|
||||
#0:RC32M,1:Xtal,2:wifipll 240M,3:wifipll 320M,4:cpupll 400M
|
||||
dsp_clk=3
|
||||
dsp_clk_div=0
|
||||
dsp_bclk_div=1
|
||||
#0:RC32M,1:Xtal,2:wifipll 160M,3:cpupll 160M,4:wifipll 240M
|
||||
dsp_pbclk=2
|
||||
dsp_pbclk_div=0
|
||||
|
||||
#0:mcu pbclk,1:cpupll 200M,2:wifipll 320M,3:cpupll 400M
|
||||
emi_clk=2
|
||||
emi_clk_div=1
|
||||
|
||||
#0:wifipll 120M,1:xtal,2:cpupll 100M,3:wifipll 80M,4:bclk,5:wifipll 96M
|
||||
flash_clk_type=1
|
||||
flash_clk_div=0
|
||||
|
||||
wifipll_pu=1
|
||||
aupll_pu=1
|
||||
cpupll_pu=1
|
||||
mipipll_pu=1
|
||||
uhspll_pu=1
|
||||
|
||||
clkcfg_crc32=0
|
||||
|
||||
########################boot cfg#####################################
|
||||
#1:ECC
|
||||
sign=0
|
||||
#1:AES128, 2:AES256, 3:AES192
|
||||
encrypt_type=0
|
||||
key_sel=0
|
||||
#0:AES CTR MODE, 1:AES XTS MODE
|
||||
xts_mode=0
|
||||
aes_region_lock=0
|
||||
no_segment=1
|
||||
boot2_enable=0
|
||||
boot2_rollback=0
|
||||
cpu_master_id=0
|
||||
notload_in_bootrom=0
|
||||
crc_ignore=1
|
||||
hash_ignore=1
|
||||
power_on_mm=1
|
||||
em_sel=1
|
||||
cmds_en=1
|
||||
#0:cmds bypass wrap commands to macro, original mode;
|
||||
#1:cmds handle wrap commands, original mode;
|
||||
#2:cmds bypass wrap commands to macro, cmds force wrap16*4 splitted into two wrap8*4;
|
||||
#3:cmds handle wrap commands, cmds force wrap16*4 splitted into two wrap8*4
|
||||
cmds_wrap_mode=2
|
||||
#0:SF_CTRL_WRAP_LEN_8, 1:SF_CTRL_WRAP_LEN_16, 2:SF_CTRL_WRAP_LEN_32,
|
||||
#3:SF_CTRL_WRAP_LEN_64, 9: SF_CTRL_WRAP_LEN_4096
|
||||
cmds_wrap_len=2
|
||||
icache_invalid=1
|
||||
dcache_invalid=1
|
||||
fpga_halt_release=0
|
||||
|
||||
########################image cfg####################################
|
||||
#flash controller offset
|
||||
group_image_offset=0x00002000
|
||||
aes_region_len=0
|
||||
|
||||
#total image len or segment count
|
||||
img_len_cnt=0x8000
|
||||
#img hash
|
||||
hash_0=0xdeadbeef
|
||||
hash_1=0
|
||||
hash_2=0
|
||||
hash_3=0
|
||||
hash_4=0
|
||||
hash_5=0
|
||||
hash_6=0
|
||||
hash_7=0
|
||||
|
||||
########################CPU M0 cfg###################################
|
||||
m0_config_enable=1
|
||||
m0_halt_cpu=0
|
||||
m0_cache_enable=0
|
||||
m0_cache_wa=0
|
||||
m0_cache_wb=0
|
||||
m0_cache_wt=0
|
||||
m0_cache_way_dis=0
|
||||
m0_reserved=0
|
||||
m0_cache_range_h=0
|
||||
m0_cache_range_l=0
|
||||
|
||||
#img RAM address or flash offset
|
||||
m0_image_address_offset=0x00002000
|
||||
m0_boot_entry=0x58000000
|
||||
m0_msp_val=0
|
||||
|
||||
########################CPU D0 cfg###################################
|
||||
d0_config_enable=1
|
||||
d0_halt_cpu=0
|
||||
d0_cache_enable=0
|
||||
d0_cache_wa=0
|
||||
d0_cache_wb=0
|
||||
d0_cache_wt=0
|
||||
d0_cache_way_dis=0
|
||||
d0_reserved=0
|
||||
d0_cache_range_h=0
|
||||
d0_cache_range_l=0
|
||||
|
||||
#img RAM address or flash offset
|
||||
d0_image_address_offset=0x00022000
|
||||
d0_boot_entry=0x58020000
|
||||
d0_msp_val=0
|
||||
|
||||
########################CPU LP cfg###################################
|
||||
lp_config_enable=1
|
||||
lp_halt_cpu=0
|
||||
lp_cache_enable=0
|
||||
lp_cache_wa=0
|
||||
lp_cache_wb=0
|
||||
lp_cache_wt=0
|
||||
lp_cache_way_dis=0
|
||||
lp_reserved=0
|
||||
lp_cache_range_h=0x58050000
|
||||
lp_cache_range_l=0x58040000
|
||||
|
||||
#img RAM address or flash offset
|
||||
lp_image_address_offset=0x00042000
|
||||
lp_boot_entry=0x58040000
|
||||
lp_msp_val=0
|
||||
|
||||
boot2_pt_table_0=0
|
||||
boot2_pt_table_1=0
|
||||
|
||||
flashCfgTableAddr=0
|
||||
flashCfgTableLen=0
|
||||
|
||||
########################patch on read################################
|
||||
patch_read_addr0=0
|
||||
patch_read_value0=0
|
||||
patch_read_addr1=0
|
||||
patch_read_value1=0
|
||||
patch_read_addr2=0
|
||||
patch_read_value2=0
|
||||
patch_read_addr3=0
|
||||
patch_read_value3=0
|
||||
|
||||
########################patch on jump################################
|
||||
patch_jump_addr0=0x20000320
|
||||
patch_jump_value0=0
|
||||
patch_jump_addr1=0x2000f038
|
||||
patch_jump_value1=0x18000000
|
||||
patch_jump_addr2=0
|
||||
patch_jump_value2=0
|
||||
patch_jump_addr3=0
|
||||
patch_jump_value3=0
|
||||
|
||||
reserved1=0
|
||||
reserved2=0
|
||||
reserved3=0
|
||||
reserved4=0
|
||||
|
||||
crc32=0xdeadbeef
|
||||
|
||||
[BOOTHEADER_GROUP1_CFG]
|
||||
magic_code=0x50414642
|
||||
revision=1
|
||||
|
||||
#########################flash cfg(ignored for group1)###############
|
||||
#########################clk cfg(ignored for group1)#################
|
||||
########################boot cfg#####################################
|
||||
#1:ECC
|
||||
sign=0
|
||||
#1:AES128,2:AES256,3:AES192
|
||||
encrypt_type=0
|
||||
key_sel=0
|
||||
xts_mode=0
|
||||
aes_region_lock=0
|
||||
no_segment=1
|
||||
boot2_enable=0
|
||||
boot2_rollback=0
|
||||
cpu_master_id=0
|
||||
notload_in_bootrom=0
|
||||
crc_ignore=1
|
||||
hash_ignore=1
|
||||
power_on_mm=0
|
||||
em_sel=0
|
||||
cmds_en=1
|
||||
cmds_wrap_mode=2
|
||||
#2:SF_CTRL_WRAP_LEN_32, 3:SF_CTRL_WRAP_LEN_64, 9: SF_CTRL_WRAP_LEN_4096
|
||||
cmds_wrap_len=2
|
||||
icache_invalid=1
|
||||
dcache_invalid=1
|
||||
fpga_halt_release=0
|
||||
|
||||
########################image cfg####################################
|
||||
#flash controller offset
|
||||
group_image_offset=0x00052000
|
||||
aes_region_len=0
|
||||
|
||||
#total image len or segment count
|
||||
img_len_cnt=0x8000
|
||||
#img hash
|
||||
hash_0=0xdeadbeef
|
||||
hash_1=0
|
||||
hash_2=0
|
||||
hash_3=0
|
||||
hash_4=0
|
||||
hash_5=0
|
||||
hash_6=0
|
||||
hash_7=0
|
||||
|
||||
########################CPU M0 cfg###################################
|
||||
m0_config_enable=1
|
||||
m0_halt_cpu=0
|
||||
m0_cache_enable=0
|
||||
m0_cache_wa=0
|
||||
m0_cache_wb=0
|
||||
m0_cache_wt=0
|
||||
m0_cache_way_dis=0
|
||||
m0_reserved=0
|
||||
m0_cache_range_h=0
|
||||
m0_cache_range_l=0
|
||||
|
||||
#img RAM address or flash offset
|
||||
m0_image_address_offset=0x00052000
|
||||
m0_boot_entry=0xD8000000
|
||||
m0_msp_val=0
|
||||
|
||||
########################CPU D0 cfg###################################
|
||||
d0_config_enable=1
|
||||
d0_halt_cpu=0
|
||||
d0_cache_enable=0
|
||||
d0_cache_wa=0
|
||||
d0_cache_wb=0
|
||||
d0_cache_wt=0
|
||||
d0_cache_way_dis=0
|
||||
d0_reserved=0
|
||||
d0_cache_range_h=0
|
||||
d0_cache_range_l=0
|
||||
|
||||
#img RAM address or flash offset
|
||||
d0_image_address_offset=0x00072000
|
||||
d0_boot_entry=0x58020000
|
||||
d0_msp_val=0
|
||||
|
||||
########################CPU LP cfg###################################
|
||||
lp_config_enable=1
|
||||
lp_halt_cpu=0
|
||||
lp_cache_enable=0
|
||||
lp_cache_wa=0
|
||||
lp_cache_wb=0
|
||||
lp_cache_wt=0
|
||||
lp_cache_way_dis=0
|
||||
lp_reserved=0
|
||||
lp_cache_range_h=0
|
||||
lp_cache_range_l=0
|
||||
|
||||
#img RAM address or flash offset
|
||||
lp_image_address_offset=0x00082000
|
||||
lp_boot_entry=0x58040000
|
||||
lp_msp_val=0
|
||||
|
||||
boot2_pt_table_0=0
|
||||
boot2_pt_table_1=0
|
||||
|
||||
flashCfgTableAddr=0
|
||||
flashCfgTableLen=0
|
||||
|
||||
########################patch on read################################
|
||||
patch_read_addr0=0
|
||||
patch_read_value0=0
|
||||
patch_read_addr1=0
|
||||
patch_read_value1=0
|
||||
patch_read_addr2=0
|
||||
patch_read_value2=0
|
||||
patch_read_addr3=0
|
||||
patch_read_value3=0
|
||||
|
||||
########################patch on jump################################
|
||||
patch_jump_addr0=0x20000320
|
||||
patch_jump_value0=0
|
||||
patch_jump_addr1=0x2000f038
|
||||
patch_jump_value1=0x18000000
|
||||
patch_jump_addr2=0
|
||||
patch_jump_value2=0
|
||||
patch_jump_addr3=0
|
||||
patch_jump_value3=0
|
||||
|
||||
reserved1=0
|
||||
reserved2=0
|
||||
reserved3=0
|
||||
reserved4=0
|
||||
|
||||
crc32=0xdeadbeef
|
||||
Loading…
Reference in New Issue
Block a user